Revisions Affected

1.1, 1.2

Details

Under certain system-level conditions where bandwidth usage is high or spikes, the DSS can experience a FIFO underflow condition causing screen tearing, flickering, or otherwise corrupted LCD data output. Each pipeline in the DSS has its own dedicated 1KB FIFO which, in certain conditions, is not large enough to sustain constant LCD data output when concurrent continuous writes to memory are being performed by other device peripherals. Therefore, system-level peak bandwidth usage must be taken into consideration in order to avoid frequent FIFO underflows from occurring. In the case of high resolution displays, typically for resolutions over 1024x768, FIFO underflows can occur regularly if no steps are taken to properly manage the DSS memory bandwidth requirements. It is recommended to perform system-level stress tests based on the end-application requirements to determine if the worst-case bandwidth consumption causes the DSS FIFO to underflow, especially when using the DSS to drive LCD panels over 1024x768 resolution. In the case where frequent FIFO underflows occur, the following workaround is required for stable operation.

Workarounds

There are three features than can be used to reduce the likelihood of experiencing a DSS underflow: EMIF Class of Service mapping, DSS FIFO merge, and L3 interconnect A9 bandwidth limit. Depending on the end application, a combination of these features can be used to allow for proper DSS operation while minimizing overall system performance impact.

EMIF Class of Service

The Class of Service feature within the EMIF allows the user to assign the DSS to a priority that is higher than the other masters within the system. This ensures that during EMIF arbitration the DSS maintains the highest possible priority. When configuring the EMIF, the DSS should be assigned to Class of Service 1 (COS1). It is recommended to use this feature anytime the DSS is being used and the DSS must always remain the only peripheral assigned to Class of Service 1 to prevent other masters from being selected before the DSS during arbitration. To assign the DSS to COS1 and enable class of service mapping on COS1, the user must write the DSS connection ID, 0x25, to the CONNID_3_COS_1 bit field and set the CONNID_COS_1_MAP_EN bit of the EMIF4D_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING register.

To limit the amount of time a DSS command will remain in the EMIF command queue, the user must modify the COS_COUNT_1 bit field in the EMIF4D_COS_CONFIG register. It is recommended to start with the COS_COUNT_1 field be set to 0x0F, which means that if a command sits in the queue for 16 clock cycles then it will be executed next. If a FIFO underflow still occurs with the COS_COUNT_1 field set to 0x0F, the user should decrease this value to further reduce the maximum latency in DSS command execution. On the other hand, the COS_COUNT_1 field can be increased to improve overall system performance as long as system stress tests show there are no DSS FIFO underflows occurring.

FIFO Merge

The FIFO merge feature will consolidate the three DSS pipeline FIFOs into a single 3KB deep FIFO. However, using the FIFO merge feature introduces some feature limitations within the DSS. By performing a FIFO merge, the DSS is limited to the use of only a single plane which makes scaling and overlay features less useful. The FIFO merge feature can be enabled by setting bit 14, FIFO_MERGE, of the DISPC_CFG register in the DSS.

L3 Interconnect A9 Bandwidth Limit

The L3 interconnect can be configured to place a bandwidth limit on the A9 core in order to prevent high-load tasks or sudden spikes in processors activity from consuming too much memory bandwidth which could result in a DSS FIFO underflow. There are two registers within the L3Fast interconnect register space that must be configured to set the A9 bandwidth limit: the NOC_200F_BWLIMITER_MODENA_INIT0_BANDWIDTH_ FRACTIONAL and NOC_200F_BWLIMITER_MODENA_INIT0_BANDWIDTH _INTEGER registers. The configuration values required for a given bandwidth limit can be calculated using the following equation where x is the desired maximum A9 bandwidth on the L3 interconnect and y is resulting bandwidth factor.

The least significant 5 bits of the bandwidth factor (y), [4:0], should be programmed into the BANDWIDTH_FRACTIONAL field of the NOC_200F_BWLIMITER_MODENA_INIT0_ BANDWIDTH_FRACTIONAL register and the remaining most significant bits should be programmed into BANDWIDTH_INTEGER field of the NOC_200F_BWLIMITER _MODENA_INIT0_BANDWIDTH_INTEGER register.

For example, if y = 0x30

BANDWIDTH_FRACTIONAL = 0x10

BANDWIDTH_INTEGER = 0x1