SPRZ408D June   2014  – June 2021 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Device and Development Support Tool Nomenclature
    2. 1.2 Revision Identification
  3. 2All Errata Listed With Silicon Revision Number
  4. 3Usage Notes and Known Design Exceptions to Functional Specifications
    1. 3.1 Usage Notes
      1. 3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval
      2. 3.1.2 DDR3/DDR3L: JEDEC Specification Violation for DDR3 RESET Signal When Implementing RTC+DDR Mode
    2. 3.2 Known Design Exceptions to Functional Specifications
      1. 3.2.1 Advisory List
      2.      Advisory 1
      3.      Advisory 2
      4.      Advisory 3
      5.      Advisory 4
      6.      Advisory 5
      7.      Advisory 6
      8.      Advisory 7
      9.      Advisory 8
      10.      Advisory 9
      11.      Advisory 10
      12.      Advisory 11
      13.      Advisory 12
      14.      Advisory 13
      15.      Advisory 14
      16.      Advisory 15
      17.      Advisory 16
      18.      Advisory 17
      19.      Advisory 19
      20.      Advisory 20
      21.      Advisory 21
      22.      Advisory 22
      23.      Advisory 24
      24.      Advisory 25
      25.      Advisory 26
      26.      Advisory 27
      27.      Advisory 28
      28.      i2223
      29.      i2224
      30.      i912
      31.      i2225
      32.      i2226
  5. 4Revision History

3.1.1 LPDDR2/DDR3: JEDEC Compliance for Minimum Self-Refresh Command Interval

When using LPDDR2 or DDR3 EMIF Self-Refresh, it is possible to violate the minimum self-refresh command interval requirement specified in the JEDEC standard LPDDR2 Specifications (JESD209-2F, June 2013) and DDR3 SDRAM Specifications (JESD79-3F, July 2010). This requirement states: "The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, it is required that at least one Refresh command (8 per-bank or 1 all-bank) is issued before entry into a subsequent Self Refresh."

To meet this minimum when using the LPDDR2 or DDR3 EMIF and Self-Refresh mode (setting PWR_MGMT_CTRL.REG_LP_MODE=2), set the PWR_MGMT_CTRL.REG_SR_TIM register to a time greater than the refresh rate of the LPDDR2 or DDR3.

For example, if the refresh rate for the DDR3 is 7.8 µs and the DDR3 is running at 303 MHz, the minimum time to ensure the above requirement is:

7.8 µs / 3.3 ns = 2363 DDR clock cycles

Thus, SR_TIM must be no less than 0x9 (4096 clocks).