SPRZ342O January   2011  – April 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

 

  1.   Abstract
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 CAN Bootloader: Internal Oscillator Tolerance is Not Sufficient for CAN Operation at High Temperatures
      3. 3.1.3 FPU32 and VCU Back-to-Back Memory Accesses
      4. 3.1.4 Caution While Using Nested Interrupts
      5. 3.1.5 Flash: MAX "Program Time” and “Erase Time” in Revision G of the TMS320F2806x Piccolo™ Microcontrollers Data Manual are only Applicable for Devices Manufactured After January 2018
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
  5. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
  6. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

VCU: Overflow Flags Not Set Properly

Revision(s) Affected

0

Details

The instructions listed in Table 5-1 do not set the VSTATUS OVFR and OVFI flags for the expected conditions. For instructions not listed in Table 5-1, the OVFR and OVFI flags are set as described in the Viterbi, Complex Math and CRC Unit (VCU) chapter of the TMS320x2806x Real-Time Microcontrollers Technical Reference Manual.

Table 5-1 Instructions Affected
INSTRUCTIONS DESCRIPTION COMMENTS 
   VCADD VR5, VR4, VR3, VR2
   VCADD VR5, VR4, VR3, VR2
|| VMOV32 VRa, mem32
   VCADD VR7, VR6, VR5, VR4
 32-bit
complex addition		 Expected behavior: OVFI and OVFR should be set if the final result overflows 32 bits. Actual behavior: If the shift-right operation (before the addition) overflows 16 bits, then OVFI or OVR is set. If the imaginary-part addition overflows 16 bits, OVFI is set.(1) 
   VCDADD16 VR5, VR4, VR3, VR2
   VCDADD16 VR5, VR4, VR3, VR2
|| VMOV32 VRa, mem32
 16 + 32 = 16-bit
complex addition		 Expected behavior: OVFI and OVFR should be set if the final 16-bit result overflows. Actual behavior: OVFR and OVFI are only set if the intermediate 32-bit calculation overflows. If only the final 16-bit result overflows, then OVFR and OVFI are not set. 
   VCDSUB16 VR6, VR4, VR3, VR2
   VCDSUB16 VR6, VR4, VR3, VR2
|| VMOV32 VRa, mem32
 16 + 32 = 16-bit
complex subtraction
(1) If the real-part addition overflows 16 bits, OVFR is not set. This is the expected behavior.

Workaround

Algorithms using these instructions should not rely on the state of the OVFR and OVFI flags to determine if overflow has occurred. Algorithms should use techniques, such as scaling, to avoid overflow. This erratum does not affect the behavior of saturation when performed by these instructions. If saturation is enabled, results that overflow will still be properly saturated.

This issue has been fixed on the Revision A silicon.