SPRZ342O January   2011  – April 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

 

  1.   Abstract
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision B Usage Notes and Advisories
    1. 3.1 Silicon Revision B Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 CAN Bootloader: Internal Oscillator Tolerance is Not Sufficient for CAN Operation at High Temperatures
      3. 3.1.3 FPU32 and VCU Back-to-Back Memory Accesses
      4. 3.1.4 Caution While Using Nested Interrupts
      5. 3.1.5 Flash: MAX "Program Time” and “Erase Time” in Revision G of the TMS320F2806x Piccolo™ Microcontrollers Data Manual are only Applicable for Devices Manufactured After January 2018
    2. 3.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
  5. 4Silicon Revision A Usage Notes and Advisories
    1. 4.1 Silicon Revision A Usage Notes
    2. 4.2 Silicon Revision A Advisories
  6. 5Silicon Revision 0 Usage Notes and Advisories
    1. 5.1 Silicon Revision 0 Usage Notes
    2. 5.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
  7. 6Documentation Support
  8. 7Trademarks
  9. 8Revision History

Advisory

Boot ROM: Boot ROM GetMode( ) Boot Option Selection

Revision(s) Affected

0

Details

DevEmuRegs in the Boot ROM is linked to an incorrect memory address, which causes the Boot ROM to read the state of the TRST pin incorrectly. This condition affects the ability of the device to boot into stand-alone/Emulation boot modes properly.

Workaround(s)

A workaround function is implemented in the OTP area (reserved for TI) which bypasses this section of the Boot ROM, executes code that correctly reads the state of the TRST pin, and branches back to the Boot ROM to continue booting.

The implemented workaround modifies the operation of the Get-Mode boot option as listed in Table 5-2.

Table 5-2 Get-Mode Boot Option Selection
OTP_KEY OTP_BMODE EXPECTED BOOT MODE BOOT MODE SELECTED
!= 0x005A x Get Mode: Flash Get Mode: Flash
0x005A 0x0001 Get Mode: SCI Get Mode: SCI
0x0004 Get Mode: SPI Get Mode: SPI
0x0005 Get Mode: I2C Get Mode: I2C
0x0006 Get Mode: OTP Get Mode: OTP
0x0007 Get Mode: CAN Get Mode: CAN
0x000B Get Mode: Flash Get Mode: Flash
Other Stand-alone boot: Get Mode: Flash
Emulation boot: Wait Boot Mode		 For both stand-alone and Emulation booting:
  • If bit 7 of Part ID of device == 0,
    Get Mode – Flash
  • If bit 7 of Part ID of device == 1,
    Wait Boot Mode
Note:

The implemented workaround needs memory locations 0x0002–0x0200 in M0 RAM to be reserved for Boot-ROM usage. Applications can reuse this memory after Boot-ROM execution is completed.

This issue has been fixed on the Revision A silicon.