SPRUJF1C November   2024  – December 2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Component Identification
      3. 1.3.3 Functional Block Diagram
      4. 1.3.4 BoosterPacks
      5. 1.3.5 Device Information
        1. 1.3.5.1 Security
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Standalone Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Tree
      3. 2.2.3 Power Status LEDs
    3. 2.3  Header Information
      1. 2.3.1 OSPI Expansion Connector
      2. 2.3.2 ADC/DAC External VREF Headers
      3. 2.3.3 FSI Header
      4. 2.3.4 EQEP Headers
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  IO Expander
    10. 2.10 Interfaces
      1. 2.10.1  Memory Interfaces
        1. 2.10.1.1 OSPI
        2. 2.10.1.2 Board ID EEPROM
      2. 2.10.2  Ethernet Interface
        1. 2.10.2.1 Ethernet PHY 0 - RGMII2 / PR0_PRU0
        2. 2.10.2.2 Ethernet PHY 1 - RGMII1 / PR0_PRU1
      3. 2.10.3  I2C
        1. 2.10.3.1 Industrial Application LEDs
      4. 2.10.4  SPI
      5. 2.10.5  UART
      6. 2.10.6  MCAN
      7. 2.10.7  SDFM
      8. 2.10.8  FSI
      9. 2.10.9  JTAG
      10. 2.10.10 Test Automation Pin Mapping
      11. 2.10.11 LIN
      12. 2.10.12 ADC and DAC
      13. 2.10.13 EQEP
      14. 2.10.14 EPWM
      15. 2.10.15 USB
    11. 2.11 BoosterPack Headers
      1. 2.11.1 BoosterPack Mode 00: Standard LaunchPad/BoosterPack Pinout
      2. 2.11.2 BoosterPack Mode 01: Servo Motor Control BoosterPacks Mode
      3. 2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode
      4. 2.11.4 BoosterPack Mode 11: C2000 DRVx BoosterPacks Mode
    12. 2.12 Pinmux Mapping
    13. 2.13 Test Points
    14. 2.14 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Compliance
  11. 6Additional Information
    1. 6.1 Revision E1 Appendix
      1. 6.1.1 TA_POWERDOWNz pulled up by VSYS_TA_3V3 which is powered by VSYS_3V3
      2. 6.1.2 USB2.0_MUX_SEL0 pulled up by R355
      3. 6.1.3 MDIO and MDC of PRU0-ICSS0 needs to be routed to both Ethernet PHYs
      4. 6.1.4 AM261_RGMII1_RXLINK and AM261_RGMII2_RXLINK to be connected to GPIO
    2. 6.2 Revision E2 Appendix
      1. 6.2.1 Revision E2 Changes from E1
      2. 6.2.2 Revision E2 Known Limitations
    3. 6.3 Revision A Appendix
      1. 6.3.1 Revision A Changes from E2
      2. 6.3.2 Revision A Errata
    4.     Trademarks
  12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
  13. 8Revision History

6.2.2 Revision E2 Known Limitations

OSPI Boot - Silicon Errata

AM261x devices have a silicon errata (errata i2479) associated with the OSPI Reset signal when the device is in OSPI boot mode. In OSPI boot mode, GPIO61 is configured by the AM261x Boot ROM as OSPI0_RESET_OUT0 to drive low at power-on in order to reset an external OSPI flash device. However, due to a reset signal management issue in the OSPI controller, this pin does not de-assert and drive high after the flash device resets. The flash device remains in reset which causes the boot to fail. The LP-AM261 showcases one workaround to this issue. The implementation details are below:

  • GPIO61/OSPI0_RESET_OUT0 is routed from the AM261x to a level translator. The level translator is disabled by default. The pull-down resistor R90 on the enable signal prevents the OSPI0_RESET_OUT0 from propagating to the OSPI0 reset logic at boot. This resistor should not be removed unless OSPI boot functionality is not desired.
  • At the OSPI0 reset logic circuit, the OSPI0_RESET_OUT0 net is held HIGH through pull-up resistor R344 to hold the net high at boot. The OSPI0 reset is triggered by the WARMRSTn signal, which drives LOW at boot and goes HIGH once power supplies are stable. The output of AND gate U27 connects to the OSPI0 flash device reset input.
  • Once boot is complete, the level translator U25 can be enabled by configuring the BP_BO_MUX_EN signal HIGH via the I2C-controlled IO Expander U23. This allows OSPI_RESET_OUT0 to be configured in software to reset the flash during an application.

LP-AM261 LP-AM261 OSPI Reset Scheme Figure 6-1 LP-AM261 OSPI Reset Scheme
For more details on this silicon errata, see the AM261x Errata Document.

For more details on hardware workarounds for this issue, see the AM261x OSPI/QSPI Boot Pin Requirements section in the AM26x Hardware Design Guidelines document.

RMII Ethernet

When running RMII Ethernet on LP-AM261 Rev E2 (and E1), 10% of packets experience RX CRC or RX AlignCode errors due to signal trace length matching rules for RMII being violated on the PCB. This issue will be fixed in the next revision of the EVM with proper data and clock trace length matching.

All other Ethernet modes and protocols do not experience this issue and are expected to function without error.