SPRUJF1C November   2024  â€“ December 2025 AM2612

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Preface: Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Component Identification
      3. 1.3.3 Functional Block Diagram
      4. 1.3.4 BoosterPacks
      5. 1.3.5 Device Information
        1. 1.3.5.1 Security
  7. 2Hardware
    1. 2.1  Setup
      1. 2.1.1 Standalone Configuration
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Tree
      3. 2.2.3 Power Status LEDs
    3. 2.3  Header Information
      1. 2.3.1 OSPI Expansion Connector
      2. 2.3.2 ADC/DAC External VREF Headers
      3. 2.3.3 FSI Header
      4. 2.3.4 EQEP Headers
    4. 2.4  Push Buttons
    5. 2.5  Reset
    6. 2.6  Clock
    7. 2.7  Boot Mode Selection
    8. 2.8  GPIO Mapping
    9. 2.9  IO Expander
    10. 2.10 Interfaces
      1. 2.10.1  Memory Interfaces
        1. 2.10.1.1 OSPI
        2. 2.10.1.2 Board ID EEPROM
      2. 2.10.2  Ethernet Interface
        1. 2.10.2.1 Ethernet PHY 0 - RGMII2 / PR0_PRU0
        2. 2.10.2.2 Ethernet PHY 1 - RGMII1 / PR0_PRU1
      3. 2.10.3  I2C
        1. 2.10.3.1 Industrial Application LEDs
      4. 2.10.4  SPI
      5. 2.10.5  UART
      6. 2.10.6  MCAN
      7. 2.10.7  SDFM
      8. 2.10.8  FSI
      9. 2.10.9  JTAG
      10. 2.10.10 Test Automation Pin Mapping
      11. 2.10.11 LIN
      12. 2.10.12 ADC and DAC
      13. 2.10.13 EQEP
      14. 2.10.14 EPWM
      15. 2.10.15 USB
    11. 2.11 BoosterPack Headers
      1. 2.11.1 BoosterPack Mode 00: Standard LaunchPad/BoosterPack Pinout
      2. 2.11.2 BoosterPack Mode 01: Servo Motor Control BoosterPacks Mode
      3. 2.11.3 BoosterPack Mode 10: BOOSTXL-IOLINKM-8 Mode
      4. 2.11.4 BoosterPack Mode 11: C2000 DRVx BoosterPacks Mode
    12. 2.12 Pinmux Mapping
    13. 2.13 Test Points
    14. 2.14 Best Practices
  8. 3Software
  9. 4Hardware Design Files
  10. 5Compliance
  11. 6Additional Information
    1. 6.1 Revision E1 Appendix
      1. 6.1.1 TA_POWERDOWNz pulled up by VSYS_TA_3V3 which is powered by VSYS_3V3
      2. 6.1.2 USB2.0_MUX_SEL0 pulled up by R355
      3. 6.1.3 MDIO and MDC of PRU0-ICSS0 needs to be routed to both Ethernet PHYs
      4. 6.1.4 AM261_RGMII1_RXLINK and AM261_RGMII2_RXLINK to be connected to GPIO
    2. 6.2 Revision E2 Appendix
      1. 6.2.1 Revision E2 Changes from E1
      2. 6.2.2 Revision E2 Known Limitations
    3. 6.3 Revision A Appendix
      1. 6.3.1 Revision A Changes from E2
      2. 6.3.2 Revision A Errata
    4.     Trademarks
  12. 7References
    1. 7.1 Reference Documents
    2. 7.2 Other TI Components Used in This Design
  13. 8Revision History

2.13 Test Points

The AM261x LaunchPad includes multiple test points to aid in hardware debug. Table 2-79 includes a list of the test points available on the LaunchPad.

Table 2-79 LP-AM261 Test Points
Test Point Designator Test Point Net Name Description
TP1 VUSB_5V0 USB Type-C 5V Input
TP2 VDD_XDS3V3 XDS110 3.3V supply
TP3 GND_XDS XDS110 isolated GND
TP4 TUSB_ADDR USB Type-C Logic Controller (U6) ADDR input
TP5 TUSB_ID USB Type-C Logic Controller (U6) ID pin
TP6 TM4C129_TCK XDS110 TCK pin
TP7 TM4C129_TMS XDS110 TMS pin
TP8 TA_RESETz_XDS Test Automation reset signal to XDS110
TP9 - XDS110 PM3 pin
TP10 TM4C129_TDI XDS110 TDI pin
TP11 TM4C129_TDO XDS110 TDO pin
TP12 VBUS_XDS_5V0 XDS110 5.0V supply
TP13 GND_XDS XDS110 isolated GND
TP14 VBUS_MICRO_AB_5V0 USB2.0 micro-AB port 5.0V VBUS supply
TP15 VREG PMIC (U28) VREG output
TP16 VSYS_3V3 PMIC (U28) BUCK1 3.3V output - system IO rail
TP17 OSPI0_CSN0 OSPI0 chip select 0
TP18 OSPI0_CLK OSPI0 clock
TP19 VCORE_1V25 PMIC (U28) BUCK3 1.25V output - AM261x core voltage
TP20 OSPI0_D7 OSPI0 data bit 7
TP21 OSPI0_D6 OSPI0 data bit 6
TP22 OSPI0_D1 OSPI0 data bit 1
TP23 OSPI0_D5 OSPI0 data bit 5
TP24 OSPI0_D0 OSPI0 data bit 0
TP25 VDD_1P8 PMIC (U28) VDD_1P8 pin
TP26 OSPI0_ECC_FAIL OSPI0 ECC Fail
TP27 VSYS_2V5 PMIC (U28) BUCK2 2.5V output
TP28 OSPI0_D3 OSPI0 data bit 3
TP29 OSPI0_D2 OSPI0 data bit 2
TP30 AM261_OSPI0_DQS OSPI0 DQS
TP31 VSYS_1V8 PMIC (U28) 1.8V LDO output
TP32 OSPI0_D4 OSPI0 data bit 4
TP33 OSPI1_D7 OSPI1 data bit 7
TP34 OSPI1_DQS OSPI1 DQS
TP35 OSPI1_D6 OSPI1 data bit 6
TP36 OSPI1_D5 OSPI1 data bit 5
TP37 OSPI1_D0 OSPI1 data bit 0
TP38 OSPI1_D3 OSPI1 data bit 3
TP39 OSPI1_D4 OSPI1 data bit 4
TP40 OSPI1_D1 OSPI1 data bit 1
TP41 OSPI1_CSN0 OSPI1 chip select 0
TP42 OSPI1_D2 OSPI1 data bit 2
TP43 OSPI1_ECC_FAIL OSPI1 ECC Fail
TP44 OSPI1_CLK OSPI1 clock
TP45 EXT1_VMON2 Ethernet Connector 0 voltage monitor
TP46 AM261_PORZ PORZ
TP47 MII1_CRS MII1 Carrier Sense
TP48 VDDA_ETH1_1V8 PHY1 1.8V supply input
TP49 ETH1_CLKOUT PHY1 CLK_OUT pin
TP50 VDDA_ETH0_1V8 PHY0 1.8V supply input
TP51 ETH0_CLKOUT PHY0 CLK_OUT pin
TP52 VSYS_5V0 USB 5.0V input power load switch (U14) output
TP53 RJ45_0_VCC PHY0 RJ-45 VCC input
TP54 RJ45_1_VCC PHY1 RJ-45 VCC input
TP55 GND GND
TP56 GND GND
TP57 TA_GPIO2 Test Automation GPIO2
TP58 AM261_SAFETY_ERRORN Safety Error output signal
TP59 AM261_WARMRSTN Warm Reset
TP60 AM261_GPIO33 GPIO33
TP61 AM261_GPIO40 GPIO40
TP62 AM261_SPI2_D0 SPI2 data bit 0
TP63 AM261_MII2_COL MII2 collision detect
TP64 AM261_UART3_RXD UART3 receive
TP65 AM261_INT_PB_GPIO124 User interrupt push button input
TP66 AM261_SPI2_CS1 SPI2 chip select 1
TP67 GND GND
TP68 GND GND
TP69 GND GND
TP70 GND GND
TP71 GND GND
TP72 GND GND
TP73 GND GND