SPRUJ85B April   2024  – January 2026

PRODUCTION DATA  

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1LaunchPad Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Security
      3. 1.3.3 BoosterPacks
      4. 1.3.4 Component Identification
    4. 1.4 Compliance
  6. 2Hardware Description
    1. 2.1  Board Setup
      1. 2.1.1 Power Requirements
        1. 2.1.1.1 Power Input Using USB Type-C Connector
        2. 2.1.1.2 Power Status LEDs
        3. 2.1.1.3 Power Tree
      2. 2.1.2 Push Buttons
      3. 2.1.3 Boot mode Selection
      4. 2.1.4 IO Expander
    2. 2.2  Functional Block Diagram
    3. 2.3  GPIO Mapping
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Memory Interfaces
      1. 2.6.1 OSPI
      2. 2.6.2 MMC
      3. 2.6.3 eMMC
      4. 2.6.4 Board ID EEPROM
    7. 2.7  Ethernet Interface
      1. 2.7.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 2.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 2.7.3 LED Indication in RJ45 Connector
    8. 2.8  I2C
    9. 2.9  Industrial Application LEDs
    10. 2.10 SPI
    11. 2.11 UART
    12. 2.12 MCAN
    13. 2.13 FSI
    14. 2.14 JTAG
    15. 2.15 TIVA and Test Automation Header
    16. 2.16 LIN
    17. 2.17 ADC and DAC
    18. 2.18 EQEP and SDFM
    19. 2.19 EPWM
    20. 2.20 BoosterPack Headers
    21. 2.21 Pinmux Mapping
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  8. 4Compliance Information
    1. 4.1 Compliance and Certifications
  9. 5Additional Information
    1.     Trademarks
    2. 5.1 Sitara MCU+ Academy
    3. 5.2 Hardware Changes from RevE2 to RevA
    4. 5.3 Known Board Changes/Issues
      1. 5.3.1 OSPI DQS and LBCLK nets swap
      2. 5.3.2 XDS110 Debugger Bricking Issue
      3. 5.3.3 eMMC CMD and CLK nets swap
  10. 6Related Documentation
    1. 6.1 Supplemental Content
  11. 7References
  12. 8Revision History

2.6.1 OSPI

The AM263Px LaunchPad has a 256 Mb OSPI Flash memory device (IS25LX256-LHLE), which is connected to the OSPI0 interface of the AM263Px SoC. The OSPI supports single data rates(SDR) and double data rates(DDR) with memory speeds up to 133MHz. The OSPI flash is powered by the 3.3V system supply.

The OSPI0_D0/D1 signals are also used for boot mode control logic. There are 10KΩ resistors used to isolate the boot mode control logic after the value is latched.

LP-AM263P OSPI Flash Interface Figure 2-13 OSPI Flash Interface

Note:

AM263P_OSPI0_DQS(UART1_RXD) and AM263P_OSPI0_LBCLK(UART1_TXD) net names are wrongly swapped in the schematics of LP-AM263P Revision E2. As per datasheet OSPI0_DQS must be connected to M3 ball pin and OSPI0_LBCLKO must be connected to L3 Ball pin. This has been corrected in Revision A of LP-AM263P.

Refer to OSPI DQS and LBCLK nets swap for more details.