SPRUJ85B April   2024  – January 2026

PRODUCTION DATA  

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1LaunchPad Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
      1. 1.3.1 System Architecture Overview
      2. 1.3.2 Security
      3. 1.3.3 BoosterPacks
      4. 1.3.4 Component Identification
    4. 1.4 Compliance
  6. 2Hardware Description
    1. 2.1  Board Setup
      1. 2.1.1 Power Requirements
        1. 2.1.1.1 Power Input Using USB Type-C Connector
        2. 2.1.1.2 Power Status LEDs
        3. 2.1.1.3 Power Tree
      2. 2.1.2 Push Buttons
      3. 2.1.3 Boot mode Selection
      4. 2.1.4 IO Expander
    2. 2.2  Functional Block Diagram
    3. 2.3  GPIO Mapping
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Memory Interfaces
      1. 2.6.1 OSPI
      2. 2.6.2 MMC
      3. 2.6.3 eMMC
      4. 2.6.4 Board ID EEPROM
    7. 2.7  Ethernet Interface
      1. 2.7.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 2.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 2.7.3 LED Indication in RJ45 Connector
    8. 2.8  I2C
    9. 2.9  Industrial Application LEDs
    10. 2.10 SPI
    11. 2.11 UART
    12. 2.12 MCAN
    13. 2.13 FSI
    14. 2.14 JTAG
    15. 2.15 TIVA and Test Automation Header
    16. 2.16 LIN
    17. 2.17 ADC and DAC
    18. 2.18 EQEP and SDFM
    19. 2.19 EPWM
    20. 2.20 BoosterPack Headers
    21. 2.21 Pinmux Mapping
  7. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  8. 4Compliance Information
    1. 4.1 Compliance and Certifications
  9. 5Additional Information
    1.     Trademarks
    2. 5.1 Sitara MCU+ Academy
    3. 5.2 Hardware Changes from RevE2 to RevA
    4. 5.3 Known Board Changes/Issues
      1. 5.3.1 OSPI DQS and LBCLK nets swap
      2. 5.3.2 XDS110 Debugger Bricking Issue
      3. 5.3.3 eMMC CMD and CLK nets swap
  10. 6Related Documentation
    1. 6.1 Supplemental Content
  11. 7References
  12. 8Revision History

2.4 Reset

Figure 2-9 shows the reset architecture of the AM263Px LaunchPad


LP-AM263P Reset Architecture

Figure 2-9 Reset Architecture

The AM263Px LaunchPad has the following resets:

  • PORz is the Power On Reset
  • WARMRESETn is the warm reset


LP-AM263P PORZ Reset Signal Tree

Figure 2-10 PORZ Reset Signal Tree

The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:

  • The 3.3V buck converter (TPS62913) power good output is driven low by having an output voltage that is below the power-good threshold.
  • The 1.2V buck converter (TPS62913) power good output is driven low by having an output voltage that is below the power-good threshold.
  • The user push button (SW2) is pressed.
  • A P-Channel MOSFET gate's signal is logic LOW which causes VGS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground. The signals that can create the logic LOW input to the PMOS gate are:
    • TA_PORZ output from the Test Automation header
    • BP_PORZ output from either of the BoosterPack sites.

The PORz signal is tied to:

  • AM263Px SoC PORz input
  • Boot mode State Driver(U4)'s output enable input
    • There is an RC filter to create a 1ms delay from GND to 3.0V such that the SOP State Driver's output enable input is low longer than the required SOP hold time following a PORz de-assertion.

There is a Test-Automation PORz Override header that enables the ability to hold TA_GPIO3 low when a jumper is installed. This enables the boot mode Control from the Test Automation Header.


LP-AM263P WARMRESETn Reset Signal Tree

Figure 2-11 WARMRESETn Reset Signal Tree

The WARMRESETn signal creates a warm reset to the MAIN domain when:

  • The user push button (SW3) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which causes VGS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain which is tied directly to ground.

The WARMRESETn signal is tied to:

  • AM263Px SoC WARMRESETN output
  • RESETN_PB signal that is created from push button + PMOS logic
  • Micro SD Load Switch control input via a 2 input AND Gate with an AM263Px SoC driven GPIO signal (GPIO122)
  • Both Ethernet PHYs reset input

The AM263Px LaunchPad also has an external interrupt to the SoC , INT1, that occurs when:

  • The user push button (SW4) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which causes VGS of the PMOS to be less than zero and so the INTn signal connects to the PMOS drain which is tied directly to ground.