SPRUJ06 October   2021

 

  1.   Trademarks
  2. 1Introduction
  3. 2Revisions and Assembly Variants
  4. 3System Description
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Interfaces and Major Component Description
      1. 3.3.1 Breakout Board Section
      2. 3.3.2 IO-Link Section Overview and Major Component Description
        1. 3.3.2.1 IO Link Transceiver TIOL111DMWR
        2. 3.3.2.2 Smart Switch TPS4H160BQPWPRQ1
        3. 3.3.2.3 Serializer SN65HVS882
        4. 3.3.2.4 INA253
        5. 3.3.2.5 LED Driver TLC59282
        6. 3.3.2.6 Signal Routing
      3. 3.3.3 Power Section
        1. 3.3.3.1 Power Input
      4. 3.3.4 Board Mating Connections
  5. 4Known Issues
    1. 4.1 Issue 1: Voltage Spike Across the TX Line of the Transceiver

3.3.2.6 Signal Routing

The Signals routed to the Breakout Board section and IO Link section are described in Table 3-3.

Table 3-3 HSE Connector Signal Routing
HSE Connector MUX IO LINK Section Breakout Board Section Test Header
PRG0_PRU0GPO0 U2 RX_1 PRG0_PRU0GPO0_HDR J2
PRG0_PRU0GPO1 RX_2 PRG0_PRU0GPO1_HDR
PRG0_PRU0GPO2 RX_3 PRG0_PRU0GPO2_HDR
PRG0_PRU0GPO3 RX_4 PRG0_PRU0GPO3_HDR
PRG0_PRU0GPO4 RX_5 PRG0_PRU0GPO4_HDR
PRG0_PRU0GPO5 RX_6 PRG0_PRU0GPO5_HDR
PRG0_PRU0GPO6 RX_7 PRG0_PRU0GPO6_HDR
PRG0_PRU0GPO7 RX_8 PRG0_PRU0GPO7_HDR
PRG0_PRU0GPO8 U4 TX_1 PRG0_PRU0GPO8_HDR
PRG0_PRU0GPO11 TX_2 PRG0_PRU0GPO11_HDR
PRG0_PRU0GPO12 TX_3 PRG0_PRU0GPO12_HDR J3
PRG0_PRU0GPO13 TX_4 PRG0_PRU0GPO13_HDR
PRG0_PRU0GPO14 TX_5 PRG0_PRU0GPO14_HDR
PRG0_PRU0GPO15 TX_6 PRG0_PRU0GPO15_HDR
PRG0_PRU0GPO16 TX_7 PRG0_PRU0GPO16_HDR
PRG0_PRU0GPO17 TX_8 PRG0_PRU0GPO17_HDR
PRG0_PRU1GPO6 U9 EN_PHY_1 PRG0_PRU1GPO6_HDR J4
PRG0_PRU1GPO8 EN_PHY_2 PRG0_PRU1GPO8_HDR
PRG0_PRU1GPO11 EN_PHY_3 PRG0_PRU1GPO11_HDR J5
PRG0_PRU1GPO12 EN_PHY_4 PRG0_PRU1GPO12_HDR
PRG0_PRU1GPO13 EN_PHY_5 PRG0_PRU1GPO13_HDR
PRG0_PRU1GPO14 EN_PHY_6 PRG0_PRU1GPO14_HDR
PRG0_PRU1GPO15 EN_PHY_7 PRG0_PRU1GPO15_HDR
PRG0_PRU1GPO16 EN_PHY_8 PRG0_PRU1GPO16_HDR
PRG0_PRU1GPO2 U7 EN_L+5 PRG0_PRU1GPO2_HDR J4
PRG0_PRU0GPO18 EN_L+1 PRG0_PRU0GPO18_HDR
PRG0_PRU0GPO19 EN_L+2 PRG0_PRU0GPO19_HDR
PRG0_PRU1GPO4 EN_L+7 PRG0_PRU1GPO4_HDR
PRG0_PRU1GPO0 EN_L+3 PRG0_PRU1GPO0_HDR
PRG0_PRU1GPO1 EN_L+4 PRG0_PRU1GPO1_HDR
PRG0_PRU1GPO3 EN_L+6 PRG0_PRU1GPO3_HDR
PRG0_PRU1GPO5 EN_L+8 PRG0_PRU1GPO5_HDR
GPMC0_ADC0 U11 FAULT_1 GPMC0_ADC0_HDR J6
GPMC0_ADC1 FAULT_2 GPMC0_ADC1_HDR
GPMC0_ADC2 FAULT_3 GPMC0_ADC2_HDR
GPMC0_ADC3 FAULT_4 GPMC0_ADC3_HDR
GPMC0_ADC4 FAULT_5 GPMC0_ADC4_HDR
GPMC0_ADC5 FAULT_6 GPMC0_ADC5_HDR
GPMC0_ADC6 FAULT_7 GPMC0_ADC6_HDR
GPMC0_ADC7 FAULT_8 GPMC0_ADC7_HDR
HSE_GPIO0_36 U12 L_FAULT HSE_GPIO0_36_HDR J8
HSE_GPIO0_35 L_SEL HSE_GPIO0_35_HDR
HSE_GPIO0_37 LOAD_PULSE_SE HSE_GPIO0_37_HDR
HSE_GPIO0_34 L_SEH HSE_GPIO0_34_HDR
HSE_GPIO0_31 H_SEH HSE_GPIO0_31_HDR
HSE_GPIO0_32 H_SEL HSE_GPIO0_32_HDR
HSE_GPIO0_33 H_FAULT HSE_GPIO0_33_HDR
HSE_GPIO0_38 HSE_GPIO0_38
HSE_GPIO0_39 HSE_GPIO0_39
HSE_GPIO0_41 HSE_GPIO0_41
SOC_SPI1_MISO U17 SOC_SPI1_MISO_SE SOC_SPI1_MISO_HDR J9
SOC_SPI1_MOSI SOC_SPI1_MOSI_LED SOC_SPI1_MOSI_HDR
SOC_SPI1_CLK SOC_SPI1_CLK_SE/LED SOC_SPI1_CLK_HDR
SOC_SPI1_CS0 SOC_SPI1_CS0_SE SOC_SPI1_CS0_HDR
SOC_SPI1_CS1 LATCH SOC_SPI1_CS1_HDR
HSE_MCAN1_RX/I2C3_SDA HSE_MCAN1_RX/I2C3_SDA J3
HSE_MCAN1_TX/I2C3_SCL HSE_MCAN1_TX/I2C3_SCL
HSE_MCAN0_TX/UART4_RXD HSE_MCAN0_TX/UART4_RXD
HSE_MCAN0_RX/UART4_TXD HSE_MCAN0_RX/UART4_TXD
GPMC0_ADC[8:9] GPMC0_ADC[8:9] J6
GPMC0_ADC[10:15] GPMC0_ADC[10:15] J7
GPMC0_CSN2 GPMC0_CSN2
GPMC0_CSN3 GPMC0_CSN3
GPMC0_CSN1 GPMC0_CSN1
GPMC0_DIR GPMC0_DIR
PRG1_PRU1GPO18 PRG1_PRU1GPO18 J5
PRG1_PRU1GPO19 PRG1_PRU1GPO19
PRG0_MDIO0_MDIO PRG0_MDIO0_MDIO
PRG0_MDIO0_MDC PRG0_MDIO0_MDC