SPRUIW3 October   2021 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   Trademarks
  2. 1Feature Differences Between F28004x and F28003x
    1. 1.1 F28004x and F28003x Feature Comparison
  3. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ Package
      1. 2.1.1 100-Pin PZ Migration for Existing PCB
      2. 2.1.2 100-Pin PZ Migration for New PCB Design
    2. 2.2 PCB Hardware Changes for the 64-Pin PM Package
      1. 2.2.1 64-Pin PM Migration for New and Existing PCB
  4. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28003x
      1. 3.1.1  TMU Type1
      2. 3.1.2  Fast Integer Division (FINTDIV)
      3. 3.1.3  Host Interface Controller (HIC)
      4. 3.1.4  Background CRC (BGCRC)
      5. 3.1.5  Standby Low Power Mode
      6. 3.1.6  X1 GPIO Functionality
      7. 3.1.7  Diagnostic Features (PBIST/HWBIST)
      8. 3.1.8  Advance Encryption Standard (AES)
      9. 3.1.9  Secure Boot/JTAG Lock
      10. 3.1.10 Modular Controller Area Network (MCAN)
      11. 3.1.11 Embedded Pattern Generator (EPG)
      12. 3.1.12 Live Firmware Update (LFU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 XTAL Module
      2. 3.5.2 PLL
      3. 3.5.3 PIE Channel Mapping
      4. 3.5.4 Bootrom
      5. 3.5.5 CLB and Motor Control Libraries
      6. 3.5.6 ERAD
      7. 3.5.7 GPIO
      8. 3.5.8 AGPIO
      9. 3.5.9 ERROR Status
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 DCDC
      3. 3.6.3 POR/BOR
      4. 3.6.4 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  5. 4Application Code Migration From F28004x to F28003x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 Minimum Compiler Version Requirement for TMU Type 1
    4. 4.4 C2000Ware Examples
  6. 5Specific Use Cases Related to F28003x New Features
    1. 5.1 HIC
    2. 5.2 FINTDIV
    3. 5.3 TMU Type1
    4. 5.4 AES
    5. 5.5 MCAN
    6. 5.6 EPG
  7. 6EABI Support
    1. 6.1 Flash API
    2. 6.2 NoINIT Struct Fix (Linker Command)
    3. 6.3 Pre-Compiled Libraries
  8. 7References

3.5.4 Bootrom

For bootrom similarities and differences between F28004x and F28003x see Table 3-8 and Table 3-11.

Table 3-8 Bootrom Comparison Table
F28004x F28003x
System Debug (ERAD) NMI is disabled NMI is enabled. Bootrom exception handler is updated for this NMI
HWBIST HWBIST is not available HWBIST is available
CPU Boot Mode GPIO Assignments On the 64-Pin package, F28004x and F28003x have similar options however the BOOTDEFx values are different. For boot mode GPIO assignment on the other packages, see Bootrom section in the device-specific data sheet.
BMSP Restrictions - Do not use pins GPIO20-33, GPIO36, GPIO38 and GPIO60-233 GPIO36, GPIO38, GPIO62-223
RAM Initialization RAM initialization occurs on POR and XRS RAM initialization occurs only on POR
ROM Table ROM tables for F28004x and F28003x are different. For details, see device-specific TRM.
PBIST(MPOST) Status Flag Flag is reset for every reset type Flag is reset only for POR rest type
PBIST(MPOST) Execution Speed Will execute either at maximum SYSCLK speed or INTOSC clock Will execute at maximum SYSCLK speed, half of maximum SYSCLK speed or INTOSC clock
Table 3-9 Boot options Legend
Color Description
Options common for both devices but BOOTDEFx values may differ
Options applicable only for F28004x
Options applicable only for F28003x
Table 3-10 Bootloaders and GPIO Assignment Comparison
Bootloader Option BOOTDEFx F28004x F28003x
Parallel 0 0x00 D0-D7=0 to 7; DSP=16; Host=11 D0-D7=0 to 7; DSP=16; Host=29
1 0x20 n/a D0-D7=0 to 7; DSP=16; Host=11
SCIA 0 0x01 TX=29; RX=28 TX=29; RX=28
1 0x21 TX=16; RX=17 TX=16; RX=17
2 0x41 TX=8; RX=9 TX=8; RX=9
3 0x61 TX=48; RX=49 TX=2; RX=3
4 0x81 TX=24; RX=25 TX=16; RX=3
CAN 0 0x02 TX=32; RX=33 TX=4; RX=5
1 0x22 TX=4; RX=5 TX=32; RX=33
2 0x42 TX=31; RX=30 TX=2; RX=3
3 0x62 TX=37; RX=35 TX=13; RX=12
MCAN 0 0x08 n/a TX=4; RX=5
1 0x28 n/a TX=1; RX=0
2 0x48 n/a TX=13; RX=12
SPI 0 0x06 n/a SIMO=2 SOMI=1; CLK=3; STE=5
1 0x26 SIMO=8; SOMI=10; CLK=9; STE=11 SIMO=16 SOMI=1; CLK=3; STE=0
2 0x46 SIMO=54; SOMI=55; CLK=56; STE=57 SIMO=8 SOMI=10; CLK=9; STE=11
3 0x66 SIMO=16; SOMI=17; CLK=56; STE=57 SIMO=8 SOMI=17; CLK=9; STE=11
4 0x86 SIMO=8; SOMI=17; CLK=9; STE=11 n/a
I2C 0 0x07 SDA=32; SCL=33 SDA=32; SCL=33
1 0x27 n/a SDA=0; SCL=1
2 0x47 SDA=26; SCL=27 SDA=10; SCL=8
3 0x67 SDA=42; SCL=43 n/a
Table 3-11 Boot Modes Comparison
Boot Mode Option BOOTDEFx F28004x F28003x
Flash 0 0x03 Entry=0x00080000; Bank/Sector=0/0 Entry=0x00080000; Bank/Sector=0/0
1 0x23 Entry=0x0008EFF0; Bank/Sector=0/14 Entry=0x00088000; Bank/Sector=0/8
2 0x43 Entry=0x00090000; Bank/Sector=1/0 Entry=0x0008FFF0; Bank/Sector=0/15
3 0x63 Entry=0x0009EFF0; Bank/Sector=1/14 Entry=0x00090000; Bank/Sector=1/0
4 0x83 - Entry=0x00097FF0; Bank/Sector=1/7
5 0xA3 - Entry=0x0009FFF0; Bank/Sector=1/15
6 0xC3 - Entry=0x000A0000; Bank/Sector=2/0
7 0xE3 - Entry=0x000AFFF0; Bank/Sector=2/15
LFU Flash 0 0x0B - Entry=0x00080000; Bank=0
Entry=0x00090000; Bank=1
Entry=0x000A0000 Bank=2
1 0x2B - Entry=0x00088000; Bank=0
Entry=0x00098000; Bank=1
Entry=0x000A8000 Bank=2
2 0x4B - Entry=0x0008FFF0; Bank=0
Entry=0x0009FFF0; Bank=1
Entry=0x000AFFF0 Bank=2
3 0x6B - Entry=0x00088000; Bank=0
Entry=0x00090000; Bank=1
Entry=0x000A0000 Bank=2
4 0x8B - Entry=0x0008EFF0; Bank=0
Entry=0x00097FF0; Bank=1
Entry=0x000A7FF0 Bank=2
Secure LFU Flash 0 0x0C - Entry=0x00080000; Bank=0
Entry=0x00090000; Bank=1
Entry=0x000A0000 Bank=2
1 0x2C - Entry=0x00088000; Bank=0
Entry=0x00098000; Bank=1
Entry=0x000A8000 Bank=2
2 0x4C - Entry=0x0008FFF0; Bank=0
Entry=0x0009FFF0; Bank=1
Entry=0x000AFFF0 Bank=2
3 0x6C - Entry=0x00088000; Bank=0
Entry=0x00090000; Bank=1
Entry=0x000A0000 Bank=2
4 0x8C - Entry=0x0008EFF0; Bank=0
Entry=0x00097FF0; Bank=1
Entry=0x000A7FF0 Bank=2
Wait 0 0x04 Watchdog enabled Watchdog enabled
1 0x24 Watchdog disabled Watchdog disabled
RAM 0 0x05 Entry=0x00000000 Entry=0x00000000