SPRUIT0A December   2019  – May 2020

 

  1.   Jacinto7 EVM Infotainment Expansion
    1.     Trademarks
    2. 1 Introduction
      1. 1.1 Key Features
    3. 2 Infotainment Expansion Board Overview
      1. 2.1 Infotainment Expansion Board Identification
      2. 2.2 Infotainment Expansion Board Component Identification
    4. 3 Infotainment Expansion Board - User Setup/Configuration
      1. 3.1 Interfacing Infotainment Expansion Board With CP Board
        1. 3.1.1 Board Assembly Procedures
      2. 3.2 Power Requirements
      3. 3.3 EVM Reset/Interrupt Push Buttons
      4. 3.4 EVM Configuration DIP Switch
    5. 4 Infotainment Expansion Board Hardware Architecture
      1. 4.1  Infotainment Expansion Board Hardware Top Level Diagram
      2. 4.2  Expansion Connectors
      3. 4.3  Board ID EEPROM
      4. 4.4  Audio Codec Interface
        1. 4.4.1 Port Mapping
      5. 4.5  FPD link De-Serializer Interface (Audio)
      6. 4.6  DIR Interface
      7. 4.7  DIT Interface
      8. 4.8  Legacy Audio/JAMR3 Connectors
      9. 4.9  VIN/VOUT Mux Selection
      10. 4.10 HDMI Interface Bridge
      11. 4.11 FPD Link Display Serializer Interface
      12. 4.12 Parallel Camera Interface
        1. 4.12.1 Camera Clock
        2. 4.12.2 LI Camera Module Connector
        3. 4.12.3 OV Camera Module Connector
  2.   A Jacinto7 EVM Interface/IO Mapping
    1.     A.1 Interface Mapping
    2.     A.2 Infotainment Board GPIO Mapping
    3.     A.3 I2C Address Mapping
  3.   Revision History

2 Infotainment Expansion Board Overview

Jacinto7 EVM can support different types of expansion boards, one of which is Infotainment. Not all the expansion boards may not be available on all Jacinto7 EVMs.

To determine version of the Jacinto7 EVM supports the Infotainment expansion board, see Section A.

Figure 1 shows the overall architecture of Jacinto7 EVM.

j721e-system-architecture-interface_2.gif
1. Only one board can be connected to Expansion connector at a time.
2. Only one board can be connected to CSI2 Expansion connector at a time.
Figure 1. System Architecture Interface