SPRACZ5 December   2021 TDA4VM

 

  1.   Trademarks
  2. 1Introduction
  3. 2Enabling Thermal Shutdown Mandatory Step
  4. 3Thermal Mitigation Strategies at a High Level
    1. 3.1 Strategy 1: Auditing the Power Domains That Contribute to the Highest Power Consumption
    2. 3.2 Strategy 2: Disable Loading of Remote Core Firmware
    3. 3.3 Strategy 3: Disabling Modules on TDA4
      1. 3.3.1 Example: Disabling PCIe Instances on 7.3
    4. 3.4 Strategy 4: Dynamic Frequency Scaling (DFS)
    5. 3.5 Strategy 5: How to Reduce Frequency of Other Cores
  5. 4References

3.1 Strategy 1: Auditing the Power Domains That Contribute to the Highest Power Consumption

Key Power domains that contribute significantly are captured in Table 3-1. (These are the highest power consuming domains and they are not in any order).

Table 3-1 Power Domain Vs Module Mapping
Power Domain Module
PD_MCU_R5FF0FSS MCU_R5FSS
PD_C71X0 MMA & C71SS
PD_A72_CLUSTER0 A72SS
PD_A72_0 A72_CORE0
PD_A72_1 A72_CORE1
PD_GPUCOM GPU
PD_CPUCORE
PD_C66x_0 C66SS_0
PD_C66x_1 C66SS_0
PD_R5FSS_0 R5FSS_0
PD_R5SS_1 R5FSS_1
PD_DECODE D5520MPx
PD_ENCODE VXE384MP2
PD_DMPAC DMPAC
PD_VPAC VPAC
  • A. Shell script to get the status of the top power consuming power domains
    k3conf dump device > devdump
cat devdump | grep -E ' 202 | 203 | 124 | 140 |  4 | 16 | 140 | 141 | 243 | 244 | 48 | 290 | 144 | 153 | 249 '

    A complete list of Device IDs can be looked up here:

    Sample output:

    root@j7-evm:~# ./high-power-pd.sh
| 4 | J721E_DEV_A72SS0 | DEVICE_STATE_ON |
| 16 | J721E_DEV_C71SS0_MMA | DEVICE_STATE_ON |
| 48 | J721E_DEV_DMPAC0 | DEVICE_STATE_OFF |
| 124 | J721E_DEV_GPU0 | DEVICE_STATE_ON |
| 140 | J721E_DEV_C66SS0 | DEVICE_STATE_ON |
| 141 | J721E_DEV_C66SS1 | DEVICE_STATE_ON |
| 144 | J721E_DEV_DECODER0 | DEVICE_STATE_OFF |
| 153 | J721E_DEV_ENCODER0 | DEVICE_STATE_OFF |
| 202 | J721E_DEV_A72SS0_CORE0 | DEVICE_STATE_ON |
| 203 | J721E_DEV_A72SS0_CORE1 | DEVICE_STATE_ON |
| 243 | J721E_DEV_R5FSS0 | DEVICE_STATE_ON |
| 244 | J721E_DEV_R5FSS1 | DEVICE_STATE_ON |
| 249 | J721E_DEV_MCU_R5FSS0 | DEVICE_STATE_ON |
| 290 | J721E_DEV_VPAC0 | DEVICE_STATE_OFF |
root@j7-evm:~#
  • B. Statically configuring the A72 core to start at 1 GHz
    Index: u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33/arch/arm/mach-k3/j721e_init.c
===================================================================
--- u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33.orig/arch/arm/mach-k3/j721e_init.c
+++ u-boot-2020.01+gitAUTOINC+2781231a33-g2781231a33/arch/arm/mach-k3/j721e_init.c
@@ -378,6 +378,10 @@ void board_init_f(ulong dummy)
     if (ret)
         panic("DRAM init failed: %d\n", ret);
 #endif
+#ifdef CONFIG_ARM64
+       int tmp;
+       tmp = set_a72_clk_frequency(1000000000);
+#endif
 }
 
 u32 spl_boot_mode(const u32 boot_device)
@@ -573,3 +577,26 @@ err_load:
     rproc_reset(2);
 }
 #endif
+
+#ifdef CONFIG_ARM64
+int set_a72_clk_frequency(u64 freq) {
+       struct ti_sci_handle *ti_sci;
+       struct ti_sci_clk_ops *clk_ops;
+       int ret = 0;
+
+       writel(0x80000001, 0x688040);
+       printf("The value of PLL8_SS_CTRL register 0x%x\n", readl(0x688040));
+       ti_sci = get_ti_sci_handle();
+       clk_ops = &ti_sci->ops.clk_ops;
+
+       ret = clk_ops->set_freq(ti_sci, 202, 2, 100000000, freq, 2000000000);
+       if (ret) {
+               printk("failed to set the frequency %d\n", ret);
+               return ret;
+       }
+
+       printk("Successfully set the clock frequency to %lld\n", freq);
+
+    return 0;
+}
+#endif