SNOU180A June   2021  – September 2021 LM74701-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Setup
    1. 2.1 I/O Connector Description
    2. 2.2 Board Setup
    3. 2.3 Schematic
  4. 3LM74701-Q1EVM Performance Capture
    1. 3.1 LM74701-Q1EVM Startup
    2. 3.2 Startup Reverse Polarity (–12 V)
    3. 3.3 ISO 7637-2 Pulse 1 Performance
  5. 4EVM Board Assembly Drawings and Layout Guidelines
    1. 4.1 PCB Drawings
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 I/O Connector Description

    VIN J1: Power input connector to the positive rail of the input power supply
    GND1 J3: Ground connection for the power supply
    VOUT J2: Power output connector to the positive side of the load
    GND2 J4: Ground connection for the load
    EN J5: Jumper to enable LM74701-Q1 gate driver
    1-2 position connects EN to Anode, 2-3 position connects EN to GND
    Test Points VINA, VOUTA,GATE,ENA,BATT_MON, GND1, and GND2 are test points
GUID-BE9FF707-E389-4713-A3E1-C023AB863A0D-low.gif Figure 2-1 LM74701-Q1EVM Typical Application Circuit