SNLU325 October   2023 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

1.1 Register Programming Through SMBus

The DS320PR410 internal registers can be accessed through the standard SMBus protocol. The SMBus secondary address is determined at power up based on the configuration of the EQ1 / ADDR1 and EQ0 / ADDR0 pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.

The EQ1 / ADDR1 and EQ0 / ADDR0 pins along with GAIN, MODE, and RX_DET pins are 5-level input pins that are used to control the configuration of the device. These 5-level inputs use a resistor divider to help set the four valid levels as provided in Table 1-1.

Table 1-1 DS320PR410 5-Level Control Pin Settings
Pin LevelPin Setting
L01 kΩ to GND
L18.25 kΩ to GND
L224.9 kΩ to GND
L375 kΩ to GND
L3F (Float)

There are 16 unique SMBus secondary addresses that can be assigned to the device by placing external resistor straps on the EQ0 / ADDR0 and EQ1 / ADDR1 pins as provided in Table 1-2. When multiple DS320PR410 devices are on the same SMBus interface bus, each device must be configured with a unique SMBus secondary address.

Table 1-2 DS320PR410 SMBus Address Map
EQ1 / ADDR1 Pin LevelEQ0 / ADDR0 Pin Level7-Bit Address [HEX]
L0L00x18
L0L10x1A
L0L20x1C
L0L30x1E
L0L4Reserved
L1L00x20
L1L10x22
L1L20x24
L1L30x26
L1L4Reserved
L2L00x28
L2L10x2A
L2L20x2C
L2L30x2E
L2L4Reserved
L3L00x30
L3L10x32
L3L20x34
L3L30x36
L3L4Reserved