SNLU297 May   2021 DS320PR810

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Applications
  3. 2Description
    1. 2.1  DS320PR810 5-Level I/O Control Inputs
    2. 2.2  DS320PR810 Modes of Operation
    3. 2.3  DS320PR810 SMBus or I2C Register Control Interface
    4. 2.4  DS320PR810 Equalization Control
    5. 2.5  DS320PR810 RX Detect State Machine
    6. 2.6  DS320PR810 DC Gain Control
    7. 2.7  DS320PR810 EVM Global Controls
    8. 2.8  DS320PR810EVM Downstream Devices Control
    9. 2.9  DS320PR810EVM Upstream Devices Control
    10. 2.10 Quick-Start Guide (Pin Mode)
    11. 2.11 Quick-Start Guide (SMBus Slave Mode)
  4. 3Test Setup and Results
  5. 4Schematics
  6. 5Board Layout
  7. 6Bill of Materials
  8. 7References

2.9 DS320PR810EVM Upstream Devices Control

Table 2-9 shows DS320PR810EVM upstream devices controls that affect US1-US2 devices on the board.

Table 2-9 EVM Upstream Devices Controls
COMPONENTNAMEFUNCTION / DESCRIPTION
J214x2 HeaderGain Controls tied to GAIN pins of all downstream device banks
L0: –6 dB Gain Setting
L1: –4 dB Gain Setting
L2: -2 dB Gain Setting
L3: +2 dB Gain Setting
L4: 0 dB Gain Setting (default)
J2217x2

Pin Mode: EQ1 controls for each upstream device and device bank.

Use pins 1–8 for configuring EQ1_0 pin of Bank 0 of US1 device.

Use pins 9–16 for configuring EQ1_1 pin of Bank 1 of US1 device.

Use pins 17–24 for configuring EQ1_0 pin of Bank 0 of US2 device.

Use pins 25–32 for configuring EQ1_1 pin of Bank 1 of US2 device.

SMBus, I2C Modes: ADDR1 controls for each upstream device.

Use pins 1–8 for configuring ADDR1 pin of US1 device.

Use pins 17–24 for configuring ADDR1 pin of US2 device.

Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to achieve L4 level on the pin.

J2317x2 Header

Pin Mode: EQ0 controls for each upstream device and device bank.

Use pins 1–8 for configuring EQ0_0 pin of Bank 0 of US1 device.

Use pins 9–16 for configuring EQ0_1 pin of Bank 1 of US1 device.

Use pins 17–24 for configuring EQ0_0 pin of Bank 0 of US2 device.

Use pins 25–32 for configuring EQ0_1 pin of Bank 1 of US2 device.

SMBus, I2C Modes: ADDR0 controls for each upstream device.

Use pins 1–8 for configuring ADDR0 pin of US1 device.

Use pins 17–24 for configuring ADDR0 pin of US2 device.

Install a shunt to achieve L0, L1, L2 or L3 level on the pin. Leave floating to achieve L4 level on the pin.

J243x1 HeaderGAIN / SDA Dual Function Pin Provision for US1 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J253x1 HeaderRX DET / SCL Dual Function Pin Provision for US1 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J263x1 HeaderGAIN / SDA Dual Function Pin Provision for US2 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes
J273x1 HeaderRX DET / SCL Dual Function Pin Provision for US2 Device Install shunt across pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in SMBus, I2C Modes