SNLA492 September   2025 TDP2004-Q1

1.   1
2.   Abstract
3.   Trademarks
4. 1Introduction
5. 2Access Methods
   1. 2.1 Pin-Strap Mode
   2. 2.2 SMBus, I2C Primary Mode
   3. 2.3 SMBus, I2C Secondary Mode
6. 3Register Mapping
   1. 3.1 Shared Registers
   2. 3.2 Channel Registers
7. 4RX Equalization Control Settings
8. 5Flat-Gain
9. 6RX Equalization and Flat Gain Selection Matrix
10. 7TDP2004-Q1 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
11. 8Summary
12. 9References