SNLA492 September   2025 TDP2004-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Access Methods
    1. 2.1 Pin-Strap Mode
    2. 2.2 SMBus, I2C Primary Mode
    3. 2.3 SMBus, I2C Secondary Mode
  6. 3Register Mapping
    1. 3.1 Shared Registers
    2. 3.2 Channel Registers
  7. 4RX Equalization Control Settings
  8. 5Flat-Gain
  9. 6RX Equalization and Flat Gain Selection Matrix
  10. 7TDP2004-Q1 Programming Example
    1. 7.1 PD Control Through Register Programming
    2. 7.2 Broadcast Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
    3. 7.3 Individual Channel CTLE Index or Flat Gain Selection Through Register Programming (CTLE Index 2, Flat Gain 0dB)
  11. 8Summary
  12. 9References

4 RX Equalization Control Settings

The TDP2004-Q1 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain profile match with wide range of channel media characteristics. The EQ profile control feature is only available in SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces.

Table 4-1 provides available equalization boost at 20Gbps (10GHz Nyquist frequency) through EQ control pins or SMBus/I2C registers. In Pin Control mode EQ1 and EQ0 pins set equalization boost for channels 0-3. In I2C mode individual channels can be independently programmed for EQ boost.

Table 4-1 Equalization Control Settings
Equalization Setting Typical EQ Boost (dB)
EQ INDEX Pin mode SMBus/I2C Mode at 10GHz
EQ1 EQ0 eq_stage1_3:0 eq_stage2_2:0 eq_profile_3:0 eq_stage1_bypass
0 L0 L0 0 0 0 1 4.0
1 L0 L1 1 0 0 1 5.0
2 L0 L2 3 0 0 1 7.0
5 L1 L0 0 0 1 0 8.0
6 L1 L1 1 0 1 0 9.0
7 L1 L2 2 0 1 0 9.5
8 L1 L3 3 0 3 0 10.0
9 L1 L4 4 0 3 0 11.0
10 L2 L0 5 1 7 0 12.0
11 L2 L1 6 1 7 0 12.5
12 L2 L2 8 1 7 0 13.5
13 L2 L3 10 1 7 0 14.5
14 L2 L4 10 2 15 0 15.0
15 L3 L0 11 3 15 0 15.5
16 L3 L1 12 4 15 0 16.5
17 L3 L2 13 5 15 0 17.0
18 L3 L3 14 6 15 0 18.0
19 L3 L4 15 7 15 0 19.0