SNAA345 December   2020 LMK5C33216

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Wander Generation
    1. 2.1 Wander Generation MTIE Option 1, G.8262 EEC Option 1
    2. 2.2 Wander Generation TDEV G.8262 EEC Option 1
    3. 2.3 Wander Generation MTIE Stratum ITU-T G.8262 EEC Option 2
    4. 2.4 Wander Generation TDEV G.8262 EEC Option 2
  4. 3 Wander Transfer
    1. 3.1 Transfer Function of the PLL for Option 1 and Option 2
    2. 3.2 Wander Transfer TDEV G.8262 Option 2
  5. 4 Wander Tolerance
    1. 4.1 Wander Tolerance G.8262 Option 1
    2. 4.2 Wander Tolerance G.8262 Option 2
  6. 5 Jitter Tolerance
    1. 5.1 Jitter Tolerance G.8262 Option 1 and Option 2
  7. 6 Phase Transient Generation
    1. 6.1 Short-Term Phase Transient Response G.8262 Option 1
    2. 6.2 Short-Term Phase Transient Response G.8262 Option 2
    3. 6.3 Phase Transient Generation With Signal Interruptions G.8262 EEC Option 1
    4. 6.4 Phase Discontinuity G.8262 Option 1
    5. 6.5 Phase Discontinuity G.8262 Option 2
  8. 7 Holdover
    1. 7.1 Holdover G.8262 Option 1
    2. 7.2 Holdover G.8262 Option 2
  9. 8 Free-Run Accuracy
    1. 8.1 Free-Run Accuracy G.8262 Option 1 and Option 2
  10. 9 Pull-In and Hold-In
    1. 9.1 Pull-In Range G.8262 Option 1 and Option 2
  11. 10Conclusion
  12. 11References

7.2 Holdover G.8262 Option 2

To meet this specification, a PLL in holdover must meet the requirements in Table 7-1 (Table 15 in the G.8262 specification). The procedure for this test is that the DUT obtains lock from IN0, which contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thus entering holdover and remains in holdover for the remainder of the test. The LMK5C33216 met this specification. The TIE plot shown in Figure 7-2 demonstrates compliance to the standard in green.

Table 7-1 Transient Response Specifications During Holdover
EEC Option 2
Applies ForS > TBD(6)
a1 (ns/s)(1)50
a2 (ns/s)(2)300
b (ns/s2)(3)4.63 × 10-4
c (ns)(4)1000
d (ns/s2)(5)4.63 × 10-4
(1) a1 represents an initial frequency offset under constant temperature conditions (±1 K)
(2) a2 accounts for temperature variations after the clock went into holdover. If there are no temperature variations, the term a2S should not contribute to the phase error.
(3) b represents the average frequency drift caused by aging. This value is derived from typical aging characteristics after 60 days of continuous operation. It is not intended to measure this value on a per day basis, as the temperature effect will dominate.
(4) The phase offset c takes care of any additional phase shift that may arise during the transition at the entry of the holdover state.
(5) d represents the maximum temporary frequency drift rate at constant temperature allowed during holdover. However, it is not required that d and b be equal.
(6) TBD: To be defined.
GUID-20201210-CA0I-MQCG-WBZR-HB9ZMGHW2WMR-low.svgFigure 7-2 Holdover Option 2 Result