SLVUCD4A November   2022  – July 2026 DRA821U , DRA821U-Q1 , TPS6594-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6. 1 System Description
  7. 2 Highlighted Products
    1. 2.1 Device Versions
  8. 3 Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  9. 4 Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  10. 5 Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  11. 6 Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  12. 7 Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  13. 8 References
  14. 9 Support Resources
  15. 10Trademarks
  16. 11Revision History

1 System Description

This design guide describes a power distribution network (PDN), PDN-2A, using a single TPS6594-Q1 PMIC and a few discrete components to power the DRA821 processor and peripherals.

Note: PDN-2A for DRA821 is recommended for designs not requiring board level isolation of the MCU power for an additional lower power mode.

The following topics are described to clarify platform system operation:

  1. PDN power resource connections
  2. PDN digital control connections
  3. Primary and secondary PMIC static NVM contents
  4. PMIC sequencing settings to support different PDN power state transitions for an advanced processor system

PMIC and processor datasheets provide recommended operating conditions, electrical characteristics, recommended external components, package details, register maps, and overall component functionality. In the event of any inconsistency between any user's guide, application report, or other referenced material, the data sheet specification is the definitive source.