SLVUC26A March   2021  – April 2021 LM53602-Q1 , LM53603-Q1 , LP8733-Q1 , TDA3MA , TDA3MV , TPS22965-Q1 , TPS54116-Q1 , TPS61240-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Platform Connection
  5. 4BOOT OTP Configuration
  6. 5OTP Memory Configuration, Static Platform Settings
  7. 6OTP Memory Configuration, Power-Up and Power-Down Sequence Settings
  8. 7Revision History

2 Device Versions

The OTP settings for the LP8733-Q1 are described in this document.

In addition, power solutions are available using TPS65919-Q1 or TPS65917-Q1 as described in the TPS65919-Q1 and TPS65917-Q1 User's Guide to Power TDA3x. See Table 2-1 to determine the recommended part number based on the DDR memory type and the Vdd_dspeve current requirement of the processor.

Texas Instruments recommends having 15% margin in the load current. Therefore the current requirements listed in Table 2-1 are 15% lower than the maximum capability of the regulator. If the Vdd_dspeve current in the application is unknown, select the TPS65919-Q1 configuration because it supports the maximum performance of the processors. For systems requiring functional safety, the TPS65919-Q1 and TPS65917-Q1 devices comply with applicable ISO 26262 ASIL-B requirements.

Table 2-1 OTP Settings Differentiation
DDR Memory Type Vdd_dspeve Current Requirement PMIC Selection Content Of OTP_REV Register
DDR3, DDR3L Vdd_dspeve < 2.55 A LP873344RHDRQ1 0x44
DDR3, DDR3L Vdd_dspeve < 3 A O919A152TRGZRQ1 See User's Guide
DDR3, DDR3L Vdd_dspeve > 3 A O917A152TRGZRQ1
DDR3L Vdd_dspeve < 2.55 A LP87332ARHDRQ1 + LP87322ERHDRQ1 0x2A, 0x2E
DDR3 Vdd_dspeve < 2.55 A LP87332ARHDRQ1 +LP87322FRHDRQ1 0x2A, 0x2F