SLVK262A February 2026 – May 2026 TPS7H5030-SEP , TPS7H5031-SEP
The TPS7H503x-SEP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of four levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 10.9μm based on nominal layer thickness as shown in Figure 5-1.
Accounting for energy loss through the degrader, copper foil, beam port window, air gap, and the BEOL stack of the TPS7H503x-SEP, the effective LET (LETEFF) at the surface of the silicon substrate and the range was determined with:
The results are shown in Table 5-1.
| Facility | Beam Energy (MeV/nucleon) | Ion Type | Degrader Steps (#) | Degrader Angle (°) | Copper Foil Width (μm) | Beam Port Window | Air Gap (mm) | Angle of Incidence | LETEFF (MeV × cm2/mg) | Range in Silicon (μm) |
|---|---|---|---|---|---|---|---|---|---|---|
| KSEE | 19.5 | 109Ag | - | - | 5 | 3-mil PEN | 60 | 0 | 49.1 | 86.6 |
| TAMU | 15 | 109Ag | 0 | 0 | - | 1-mil Aramica | 40 | 0 | 47.7 | 94.2 |