2 Single-Event Effects (SEE)

The primary concern for the TPS7H3XX4-SP is the robustness against the Destructive Single-Event Effects (DSEE): Single-Event Latch-up (SEL), Single-Event Burnout (SEB), and Single-Event Gate Rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H3XX4-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1, 2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. During the testing of the TPS7H3XX4-SP a total of twelve units were exposed under worst-case bias conditions for SEL. The TPS7H3XX4-SP did not exhibit any SEL with heavy-ions with LET_EFF = 75 MeV×cm²/mg at flux of ≈1 × 10⁵ ions/cm² ×s, fluence of ≈10⁷ ions/cm², and a die temperature of 125°C.

The TPS7H3XX4-SP was evaluated for SEB/SEGR at a maximum voltage of 14V (V_IN) in the enabled and disabled states, with a total of twelve units being tested. Because it has been shown that the MOSFET susceptibility to burnout decreases with temperature [5], the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H3XX4-SP is SEB/SEGR-free up to LET_EFF = 75 MeV×cm²/mg at a flux of ≈1 × 10⁵ ions/cm²×s, fluence of ≈10⁷ ions/cm², and a die temperature of ≈25°C.

The TPS7H3XX4-SP was tested under nominal input conditions for SET. During the testing of twelve devices, not a single transient was recorded, showing that the TPS7H3XX4-SP is both transient free and SEFI free. To see more details please refer to Section 8.

The forcing conditions for the different DSEE and SET testing are shown in Table 2-1.

With SR_UVLO forced to 1V the device was in the enabled state with all RESETS high and in the disabled state with all RESETS low when forced to 0V.