SLUUCK2A October   2022  – November 2022 BQ25620 , BQ25622

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 General Descriptions
  4. 2Testing Procedures
    1. 2.1 Equipment
    2. 2.2 Hardware Setup
    3. 2.3 Software Setup
    4. 2.4 Test Procedure
      1. 2.4.1 Initial Power Up
      2. 2.4.2 I2C Register Communication Verification
      3. 2.4.3 Charger Mode Verification
      4. 2.4.4 Boost Mode Verification
      5. 2.4.5 Helpful Tips
  5. 3PCB Layout Guideline
  6. 4Board Layout, Schematic, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  7. 5Revision History

3 PCB Layout Guideline

Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the components minimizing high-frequency current path loop is important to prevent electrical and magnetic field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the order presented for proper layout:

  1. For lowest switching noise during forward/charge mode, place the decoupling PMID capacitor and then bulk PMID capacitor positive terminals as close as possible to PMID pin. Place the capacitor ground terminal close to the GND pin using the shortest copper trace connection or GND plane on the same layer as the IC.
  2. For lowest switching noise during reverse/OTG mode, place the SYS output capacitors' positive terminals near the SYS pin. The capacitors' ground terminals must be via'd down through multiple vias to an all ground internal layer that returns to IC GND pin through multiple vias under the IC.
  3. Since REGN powers the internal gate drivers, place the REGN capacitor positive terminal close to REGN pin to minimize switching noise. The capacitor's ground terminal must be via'd down through multiple vias to an all ground internal layer that returns to IC GND pin through multiple vias under the IC.
  4. Place the VBUS and BAT capacitors' positive terminals as close to the VBUS and BAT pins as possible. The capacitors' ground terminals must be via'd down through multiple vias to an all ground internal layer that returns to IC GND pin through multiple vias under the IC.
  5. Place the inductor input pin near the positive terminal of the SYS pin capacitors. Due to the PMID capacitor placement requirements, the inductor's switching node terminal must be via'd down with multiple via's to a second internal layer with a wide trace that returns to the SW pin with multiple vias. Using multiple vias ensures that the via's additional resistance is negligible compared to the inductor's dc resistance and therefore does not impact efficiency. The vias additional series inductance is negligible compared to the inductor's inductance.
  6. Place the BTST capacitor on the opposite side from the IC using vias to connect to the BTST pin and SW node.
  7. A separate analog GND plane for non-power related resistors and capacitors is not required if those components are placed away from the power components traces and planes.
  8. Ensure that the I2C SDA and SCL lines are routed away from the SW node.

Additionally, it is important that the PCB footprint and solder mask cover the entire length of each of the pins. GND, SW, PMID, SYS and BAT pins extend further into the package than the other pins. Using the entire length of these pins reduces parasitic resistance and increases thermal conductivity from the package into the board.

See the EVM design for the recommended component placement with trace and via locations.