SLUUCK2A October   2022  – November 2022 BQ25620 , BQ25622

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 EVM Features
    2. 1.2 General Descriptions
  4. 2Testing Procedures
    1. 2.1 Equipment
    2. 2.2 Hardware Setup
    3. 2.3 Software Setup
    4. 2.4 Test Procedure
      1. 2.4.1 Initial Power Up
      2. 2.4.2 I2C Register Communication Verification
      3. 2.4.3 Charger Mode Verification
      4. 2.4.4 Boost Mode Verification
      5. 2.4.5 Helpful Tips
  5. 3PCB Layout Guideline
  6. 4Board Layout, Schematic, and Bill of Materials
    1. 4.1 Board Layout
    2. 4.2 Schematic
    3. 4.3 Bill of Materials
  7. 5Revision History

4.1 Board Layout

The following figures illustrate the PCB board layers.

GUID-20221003-SS0I-0HLZ-R6LW-DHGC4PSM6CPP-low.gif Figure 4-1 BMS050 Top Layer
GUID-20221003-SS0I-6ZK6-XHRM-TNGFCGPBJLKN-low.gif Figure 4-2 BMS050 Internal Layer 1
GUID-20221003-SS0I-SR8C-GM22-6XJ1KZGHBQC1-low.gif Figure 4-3 BMS050 Internal Layer 2
GUID-20221003-SS0I-W53S-QS78-CX0Q0R0GJQXQ-low.gif Figure 4-4 BMS050 Bottom Layer