SDAA295 March   2026 DS90LV012A

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2DP/eDP Link Training Procedure and Debugging Methodology
    1. 2.1 Link Training Procedure
    2. 2.2 Debug Guide for Link Training Failure
      1. 2.2.1 Debugging Points when Clock Recovery is Not Successful
      2. 2.2.2 Debugging Points when Channel Equalization is Not Successful
      3. 2.2.3 Debugging Points when Symbol Lock and Inter-Lane Alignment is Not Successful:
  6. 3DP/eDP AUX Channel Signal Overview
    1. 3.1 AUX Transaction Types
    2. 3.2 DPTX and DPRX AUX Design Guidance
      1. 3.2.1 DP/eDP Implementation
      2. 3.2.2 Electrical Specifications
      3. 3.2.3 AUX EYE Diagram
  7. 4Decoding AUX Channel Signal
    1. 4.1 AUX Transaction Syntax
    2. 4.2 How To Use DS90LV011-12AEVM to Capture DP/eDP AUX Channel Signal
    3. 4.3 AUX Channel Decoding Methodology
    4. 4.4 AUX Channel Decoding Example
  8. 5Summary
  9. 6References

3.2.2 Electrical Specifications

Table 3-1 lists AUX Channel electrical specifications at typical condition (T=25oC, nominal VDD). See DP v1.4a and eDP v1.4b specifications for a complete table.

Table 3-1 AUX_CH Electrical Specifications
Symbol Parameter Min Nom Max Units
UIMAN Manchester transaction unit interval 0.4 0.5 0.6 us
Pre-charge pulse Number of pre-charge pulses 10 16
Number of Pulses before SYNC end symbol (DP mode) 16 pulses
Number of Pulses before SYNC end symbol (eDP mode) 8 pulses
TAUX-BUS-PARK AUX_CH bus park time 10 ns
Tcycle-to-cycle jitter Maximum allowable UI variation within a single transaction at connector pins of a transmitting device 0.08 UI
Maximum allowable variation for adjacent bit times within a single transaction at connector pins of a transmitting device 0.04 UI
Maximum allowable UI variation within a single transaction at connector pins of a receiving device 0.1 UI
Maximum allowable variation for adjacent bit times within a single transaction at connector pins of a receiving device 0.05 UI
VAUX-DIFFP-P_TX (eDP) AUX Peak-to-peak voltage at TX package pins (TP1) 0.18 0.20 1.38 V
AUX peak-to-peak voltage at TP3 0.14 1.36 V
VAUX-DIFFP-P_TX (DP) AUX peak-to-peak voltage from Main-Link Source/Sink when transmitting 0.29 0.40 1.38 V
VAUX-DIFFP-P_RX (DP) AUX peak-to-peak voltage received by Main-Link Source, TP2 0.27 1.36 V
AUX peak-to-peak voltage received by Main-Link Sink, TP3 0.27 1.36 V
VAUX-DC-CM (eDP) AUX DC common mode voltage 0 1.2 V
VAUX-DC-CM (DP) AUX DC common mode voltage 0 2.0 V
VAUX-TURN-CM AUX turnaround common mode voltage 0 0.3 V
IAUX_SHORT AUX short circuit current limit 90 mA
CAUX AUX AC-coupling capacitor 75 200 nF