SDAA195 January   2026 LMG3522R030

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Operating Principles in a Flying Capacitor Switching Cell
    1. 2.1 Switching Pattern of a 3-Level Flying Capacitor Switching Cell
  6. 3Design Considerations of a Flying Capacitor Switching Cell
    1. 3.1 Conduction and Switching Losses
      1. 3.1.1 AC Conduction Losses
      2. 3.1.2 AC Switching Losses
    2. 3.2 Passive Components Design
      1. 3.2.1 Boost Inductor Design
      2. 3.2.2 DC Link High Frequency Ripple
      3. 3.2.3 Flying Capacitor Design
    3. 3.3 Layout Considerations
    4. 3.4 Pre-Charging Network
  7. 4Experimental Results
    1. 4.1 Pre-charging of the Flying Capacitor of TIDA-010957
    2. 4.2 Steady State Operation
  8. 5Summary
  9. 6References

2.1 Switching Pattern of a 3-Level Flying Capacitor Switching Cell

As can be seen from Figure 2-1, there are four switches implemented for each phase (S1, S2, S3 and S4). In this topology, each of the FET is rated for half the DC link voltage. Though there are various switching schemes to control this power stage, a simpler scheme has been selected to reduce complexity. In this design, all the transistors are switching at the nominal frequency of fSW. Dead-time, carrier and duty cycle needs to be defined for each FET:

  • Switch pairs S1+S4, and S2+S3 are switching complementary to each other's. Two pairs of dead times are required per switching cell. If S1 and S4 are not complementary to each there is risk of shorting CDC, thus causing a severe overcurrent plus overvoltage across S2 and S3. If S2 and S3 are not switching complementary to each other there is risk of shorting CFC, thus causing a severe overcurrent plus overvoltage across S1 and S4.
  • S1+ S4 and S2+ S3 signals are 180 degrees phase-shifted to each other. Because of this phase shifting, the switching node inductor sees double the switching frequency, thus making the required inductance value smaller.
  • At first approximation the duty cycle applied to the two PWM pairs is going to be the same. The duty-cycle is as a ratio between VSW and VDC.

Three different operating points of the switching cell are investigated. The duty cycle is defined as the on time of S1 and S2:

  • When the duty cycle is higher than 50 %, S1 and S2 are more time in the on-state than S3 and S4. When there is a 1000V DC link, the output switching voltage is switching between the levels 500V and 1000V.
  • When the duty cycle is lower than 50 %, S3 and S4 are more time in the on-state than S1 and S2. When there is 1000V DC link, the output switching voltage is switching between the levels 0V and 500V.
  • When the requested duty is equal to 50 %, the four switches are going to be ON 50 % of the switching time. At first approximation, output switching node voltage is going to be fixed at 500V.

The switching pattern graphs of 3-level flying capacitor converter can be seen from section 2.2.1 of the TIDA-010957 design guide.