As demonstrated in Section 3.2, it can be observed from the formula that by switching at a higher switching frequency the flying capacitor and the boost inductor values can be decreased significantly. To achieve a higher switching frequency, GaN transistors can be adopted. These transistors switch faster than standard Si FETs, thus decreasing the switching losses. Switching faster leads to high di/dt which together with the loop parasitic inductance can lead to important device overvoltage. The overvoltage causes EMI issues or even the device destruction. In this topology, two commutation loops can be identified as in Figure 3-9.

Note the flying capacitors are not shown in Figure 3-10. Only the decoupling ceramic capacitors are shown. The blue arrows represent the inner loop, which is composed of the parasitic inductance of S2, S3, and C1. This layout can be optimized by following the layout recommendation as shown in the datasheet of LMG3522R030. The red circle represents the external loop, which is composed of S1, S4, and C3. To decouple out the parasitic inductances of S2 and S3, the capacitor C2 can be placed in parallel to C1. Having this additional capacitor allows to improve the local layout and the FETs are spread out without impacting the power performance. A recommendation layout for a three-level flying capacitor switching cell is shown in Figure 3-10.

Note that from this picture that by adding the capacitor C2 the parasitic inductance of the switching loop is decreased. When adding additional components, as a result it becomes complicated handle gate driver signals due to a larger mechanical dimension of the board. This can cause the need of derating the switching speed of the FETs, thus increasing the total losses. This can be solved by using GaN transistors with integrated gate driver as LMG3522R030. Driving the GaN transistor quickly is possible because of the internal gate driver design.