SDAA161 December   2025 TMS320F280025C , TMS320F280037C , TMS320F280039C , TMS320F280041C , TMS320F280049C , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Overview
  6. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
  7. 4EPWM Configurations
    1. 4.1 Test Results
  8. 5Summary
  9. 6References

4.1 Test Results

The design has been validated with the LaunchPad LAUNCHXL-F280039C, and Kingst Logic Analyzer, as shown in Figure 4-1.

Test Platform Setup Figure 4-1 Test Platform Setup

Figure 4-2 shows the test results during positive cycle, where EPWM5A starts CBC protection right at the fault event, while EPWM1B turns low after a delay of 2.098us measured, with 2us setting in CLB. The actual delay is a bit longer than the defined value due to the inherent delay with CLB hardware logic circuits. Figure 4-3 shows the fault event during a negative cycle, where the delayed protection logic also works as expected.

Fault Active Low During Positive Cycle Figure 4-2 Fault Active Low During Positive Cycle
Fault Active Low During Negative Cycle Figure 4-3 Fault Active Low During Negative Cycle