SDAA161 December   2025 TMS320F280025C , TMS320F280037C , TMS320F280039C , TMS320F280041C , TMS320F280049C , TMS320F28379D , TMS320F28379S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Design Overview
  6. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
  7. 4EPWM Configurations
    1. 4.1 Test Results
  8. 5Summary
  9. 6References

3.3 CLB Output

The magic of CLB output is the ability to override the original peripheral signals with the signals generated by CLB. In this case, the output LUT is used to combine the FSM_S0 and original EPWM1A/B dead-band output with AND logic. OUTPUT LUT_0 and LUT_2 is selected to enabled the AND logic output as the final EPWM1A/EPWM1B output, as listed in Figure 3-3.

CLB Output and Peripheral Signal Multiplexer Table Figure 3-3 CLB Output and Peripheral Signal Multiplexer Table

Figure 3-4 shows the relationship of the EPWM submodule signals and CLB logic.

Relationship of EPWM Submodule Signals and CLB Logic Figure 3-4 Relationship of EPWM Submodule Signals and CLB Logic