SBOA443 March   2021 INA293

 

  1.   Trademarks
  2. 1Introduction
  3. 2The SAR ADC Switching Model
    1. 2.1 Acquisition Time
    2. 2.2 ADC Resolution
    3. 2.3 Sample Rate
  4. 3The ADC Charge Bucket Filter
    1. 3.1 The Filter Capacitor, CFILT
    2. 3.2 Output Filter Resistor, RFILT
  5. 4Output Filter Discussion and Design
    1. 4.1 INA293 With the ADC Switching Model
  6. 5Summary
  7. 6References

3.1 The Filter Capacitor, CFILT

Recall that for a capacitor, the charge stored is equal to the voltage present on the capacitor multiplied by the capacitance. Then, for the sample and hold capacitor internal to the ADC, it can be expressed that

Equation 2. GUID-20210223-CA0I-KB8J-CK1F-MT0STP3DM97F-low.gif

Using this expression, CSH is defined as the internal sample and hold capacitance value of the ADC, and VFSR as the maximum possible voltage of the full scale range across CSH. The corresponding Coulumb product then gives us the maximum possible Coulombs that CSH could need to charge to within a single acquisition cycle.

When the switch of the sample and hold structure closes, charge from the current sense amplifier as well as charge held on the filter capacitor both move to charge the sample and hold structure. It can threrefore be epxressed that

Equation 3. GUID-20210223-CA0I-7B5Z-MHCC-L4MX8P7TCKCD-low.gif

While the charge delivered by the amplifier comes from its output stage, charge from the filter capacitor is depleted, and causes the voltage on the node to droop. Here, the assumption is made that half of the charge needed to charge CSH is sourced from the filter capacitor. The general form of this equation is given as

Equation 4. GUID-20210223-CA0I-PQH0-F0FX-Z7XXTP3NFD8S-low.gif

where here, N = 0.5. As the capacitance of the chosen filter capacitor is a fixed value, we can then attribute the change in charge to the droop in voltage as

Equation 5. GUID-20210223-CA0I-PZRG-P3HR-RWHHTVT32JT8-low.gif

Combining these expressions, and solving for CFILT, a final expression is derived of

Equation 6. GUID-20210223-CA0I-PDCH-4NLF-41PS6QSR224V-low.gif

By the assumptions of VFSR = 4.096V ≅ 4V, and VDROOP = ΔVFILT = 100mV, the parenthetical term reduces to a coefficient that provides a sizing relationship for the filter capacitor of

Equation 7. GUID-20210223-CA0I-3BS3-KSFW-LSZWFQVC8F2W-low.gif

This implies that for the given sample and hold capacitance of an ADC operating at a full scale range of 4V, to maintain less than 100mV droop on the input node, a filter capacitor 20 times the size of sample and hold capacitance should be mounted, provided the amplifier is capable of supplying the remaining charge. If this is not the case, the droop may be greater than the assumed 100mV, which may or may not be acceptable based on system specifications.

A capacitor of this magnitude will often be difficult to implement, as amplifiers typically cannot drive large capacitive loads on their own and maintain stability. Current sense amplifiers are no exception here, so ways to ensure stability will need to be examined to successfully drive this type of load.