SBOA443 March   2021 INA293

 

  1.   Trademarks
  2. 1Introduction
  3. 2The SAR ADC Switching Model
    1. 2.1 Acquisition Time
    2. 2.2 ADC Resolution
    3. 2.3 Sample Rate
  4. 3The ADC Charge Bucket Filter
    1. 3.1 The Filter Capacitor, CFILT
    2. 3.2 Output Filter Resistor, RFILT
  5. 4Output Filter Discussion and Design
    1. 4.1 INA293 With the ADC Switching Model
  6. 5Summary
  7. 6References

2 The SAR ADC Switching Model

When digitizing an analog signal via an ADC, the typical goal is to drive the signal to within 1/2 an LSB inside a specified period of acquisition time. This is due to the fact that the best case error that can be achieved in an ADC is limited to this value, due to the phenomenon commonly called quantization noise.

When choosing an input driver for the front end of an ADC, to meet this goal, typically three major criterion from the ADC govern the beginning focus area of analysis: acquisition time, ADC resolution, and desired sampling rate. These factors all contribute to the needs of the driver to properly drive the inputs.