SBAU434B November   2025  – April 2026 ADS125P08

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 EVM Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Analog Inputs
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Digital Interface
    4. 2.4 Power Supplies
    5. 2.5 Voltage Reference
    6. 2.6 Clocking
    7. 2.7 Using the ADS125P08 EVM With an External Controller
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS125P08 GUI Installation
  10. 4Implementation Results
    1. 4.1 Hardware Connections
    2. 4.2 GUI Operation
      1. 4.2.1 ADC Capture Settings and Sequencer Configuration
      2. 4.2.2 Time-Domain Display
      3. 4.2.3 Frequency-Domain Display
      4. 4.2.4 Histogram Display
      5. 4.2.5 EVM Register Settings
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Revision History

2.3 Digital Interface

As noted in Section 1.1, the EVM interfaces with the PHI and communicates with the computer over the USB. The PHI communicates with two devices on the EVM: the ADS125P08 (over SPI) and the EEPROM (over I2C). The EEPROM comes preprogrammed with the information required to configure and initialize the ADS125P08 platform. When the hardware is initialized, the EEPROM is no longer used

The ADS125P08 requires SPI serial communication such that CPOL = 0 and CPHA = 1. Header J4, shown in Figure 2-3, provides test points to probe the digital signals with a logic analyzer. Additionally, jumper J4 can be used to connect communication signals from an external controller. Remove the PHI controller card from connector J1 before applying external signals to jumper J4.

ADS125P08EVM-PDK EVM Digital Interface and EEPROM Figure 2-3 EVM Digital Interface and EEPROM

Similar to Figure 2-2, each digital pin has a 49.9Ω series resistor near the driving source. These resistors smooth the edges of the digital signals to provide minimal overshoot and ringing. Although not strictly required, these components can be included in the final design to improve digital signal integrity.

Figure 2-3 also shows that jumper JP1 connects the PHI_IOVDD and IOVDD nets. By default, the PHI_IOVDD net provides 3.3V to the ADC digital supply (IOVDD) pin through jumper JP1. Remove the shunt on JP1 and apply a current meter (ammeter) to measure the digital current consumed by the ADC. If desired, removing the shunt on jumper JP1 also enables connection of an external IOVDD power source to pin 1 of jumper JP1. Verify that the IOVDD voltage applied to pin 1 of jumper JP1 is the same as the I/O voltage used by the PHI or the external controller, if applicable.