SBAU434B November   2025  – April 2026 ADS125P08

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 EVM Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Analog Inputs
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Digital Interface
    4. 2.4 Power Supplies
    5. 2.5 Voltage Reference
    6. 2.6 Clocking
    7. 2.7 Using the ADS125P08 EVM With an External Controller
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS125P08 GUI Installation
  10. 4Implementation Results
    1. 4.1 Hardware Connections
    2. 4.2 GUI Operation
      1. 4.2.1 ADC Capture Settings and Sequencer Configuration
      2. 4.2.2 Time-Domain Display
      3. 4.2.3 Frequency-Domain Display
      4. 4.2.4 Histogram Display
      5. 4.2.5 EVM Register Settings
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Revision History

4.2.1 ADC Capture Settings and Sequencer Configuration

Figure 4-3 shows how the Pages control in the upper-left corner allows access to the other pages in the GUI. Navigate to any of the GUI pages using these controls. Figure 4-3 also shows the ADC Capture page. Use this page to easily configure the most important ADC settings, including the General Configuration and Step Configuration parameters, the sequencer mode, and the number of samples or sequences to capture.

ADS125P08EVM-PDK ADS125P08 EVM GUI ADC Capture Page - General ConfigurationFigure 4-3 ADS125P08 EVM GUI ADC Capture Page - General Configuration

The General Configuration tab allows to user to set certain parameters that are used for all steps, including the speed mode, the internal reference voltage, the state of the reference buffer, the state of the input buffer, and the Test DAC range. Additionally, the user can enter the External Reference Voltage if applicable. Finally, the “Ready” box indicates if the GUI is ready to communicate to the ADC (in blue) or if the GUI is busy communicating with the ADC (in orange).

The default option in the sequencer mode dropdown in Figure 4-4 allows the user to capture n conversions of a single step, where n is the number entered in the box in the lower left of the GUI. Alternatively, enable the sequencer to capture n complete sequences of all enabled steps.

Figure 4-4 shows the Step Configuration tab. Use these controls to configure the settings for each individual step. When the sequencer is disabled, only Step 0 is shown.

ADS125P08EVM-PDK ADS125P08 EVM GUI ADC Capture Page - Step ConfigurationFigure 4-4 ADS125P08 EVM GUI ADC Capture Page - Step Configuration

Table 4-1 explains in more detail each field shown in #P_O43_QGR_1HC:

Table 4-1 Understanding the Step Configuration Page Parameters

ITEM #

PARAMETER

DESCRIPTION

1

REF_SEL

Select the reference voltage source to be used with this step

2

AINP

Select the measurement channel for the positive input for this step

3

AINN

Select the measurement channel for the negative input for this step

4

SYS_MON

Select the system monitor option to be measured in this step

NOTE: the system monitor takes precedence over the AINP and AINN selections (see #2 and #3 above), and also uses the internal reference regardless of the selection in REF_SEL

5

FLTR_OSR

Select the OSR for this step

NOTE: the data rate corresponding to this OSR is shown on the right (see #10 below)

6

Step Filter Mode

Select the filter mode for this step

7

Delay in Tmods

Enter the programmable delay used for this step

NOTE: The delay value is measured in modulator clock periods (tMOD), where the modulator clock is selected by the SPEED_MODE field on the General Configuration tab

8

TDAC_SEL

Select the location where the Test DAC voltage is output to in this step

9

Test DAC (5-bit)

Select the Test DAC voltage to be used for this step

NOTE: Enter a value between 0 and 31, which is calculated in volts in the "Test DAC (V)" field on the right (see #13 below)

10

Data Rate (SPS)

Data rate relative to the selected OSR (see #5 above) and the SPEED_MODE, assuming the internal oscillator is used

NOTE: Select the SPEED_MODE on the General Configuration tab

11

Latency (μs)

Calculates the first conversion latency in microseconds

NOTE: First conversion latency includes the complete digital filter settling resulting from the FLTR_OSR and Step Filter Mode fields, as well as any additional delay entered in the Delay in Tmods field, if applicable

12

Full Scale VoltageCalculates the full-scale voltage (FSV) for this step

13

Test DAC (V)

Calculates the TDAC voltage in volts, where TDAC = TDAC_VAL * TDAC_RANGE

NOTE: Set TDAC_VAL on the Step Configuration tab and set TDAC_RANGE on the General Configuration tab

Enable the ADC sequencer by selecting "Sequencer enabled: continuous mode" from the SEQ_MODE dropdown on the General Configuration tab. Multiple step options appear after selecting this configuration. Additionally, the Capture parameter changes from "Samples" to "Sequences". As a result, the GUI captures and displays the data for the desired number of sequences defined by the user. Figure 4-5 shows how the GUI changes after enabling the sequencer.

ADS125P08EVM-PDK ADS125P08 EVM GUI ADC Capture Page - Enable SequencerFigure 4-5 ADS125P08 EVM GUI ADC Capture Page - Enable Sequencer

After enabling the sequencer, Figure 4-6 shows how clicking on each individual step opens up a new step tab. Clicking on the same step again closes that step tab. This is true for all steps except Step 0, which cannot be disabled.

ADS125P08EVM-PDK ADS125P08 EVM GUI ADC Capture Page - Enabling Multiple Sequence StepsFigure 4-6 ADS125P08 EVM GUI ADC Capture Page - Enabling Multiple Sequence Steps

Configure each enabled step as shown in Figure 4-7 and described in Table 4-1. Enabling the sequencer also enables the NUM_CONV control on each step page. The NUM_CONV control allows the user to select a specific number of consecutive conversions on that step, instead of taking a single conversion and then immediately switching to the next step. However, the GUI limits the number of sequences to one if the user selects NUM_CONV > 1 on any step page. Figure 4-7 shows this behavior, including a note in the GUI that explains how this limitation is a result of the GUI and not the ADC.

ADS125P08EVM-PDK ADS125H18 EVM GUI ADC Capture Page - Number of Conversions FieldFigure 4-7 ADS125H18 EVM GUI ADC Capture Page - Number of Conversions Field