SBAU434B November   2025  – April 2026 ADS125P08

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 EVM Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Analog Inputs
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Digital Interface
    4. 2.4 Power Supplies
    5. 2.5 Voltage Reference
    6. 2.6 Clocking
    7. 2.7 Using the ADS125P08 EVM With an External Controller
  9. 3Software
    1. 3.1 Software Description
    2. 3.2 ADS125P08 GUI Installation
  10. 4Implementation Results
    1. 4.1 Hardware Connections
    2. 4.2 GUI Operation
      1. 4.2.1 ADC Capture Settings and Sequencer Configuration
      2. 4.2.2 Time-Domain Display
      3. 4.2.3 Frequency-Domain Display
      4. 4.2.4 Histogram Display
      5. 4.2.5 EVM Register Settings
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Revision History

2.7 Using the ADS125P08 EVM With an External Controller

The ADS125P08 EVM is designed for easy connection to an external controller. This design enables the user to test application code and firmware on the ADS125P08 without having to develop a custom PCB. This section describes the specific connections required to use the ADS125P08 EVM with an external controller. Figure 2-7 shows the location of various headers, connectors, and terminal blocks described in this section.

ADS125P08EVM-PDK Connecting an External Controller to the ADS125P08 EVMFigure 2-7 Connecting an External Controller to the ADS125P08 EVM

Complete the following steps to prepare the ADS125P08 EVM for use with an external controller:

  1. Remove the PHI board if still connected to the EVM
  2. Connect the external controller ground and bench supply ground to the GND pins on the EVM
  3. Connect an external bench supply to the ADC AVDD pin by performing only one of the following two options:
    1. Remove the shunt on JP2 and apply 5.5V to the “LDO_IN” pin on JP2
    2. Remove the shunt on JP3 and apply the AVDD voltage to the “AVDD” pin on JP3
  4. Connect an external bench supply to the ADC IOVDD pin by removing the shunt on JP1 and applying the IOVDD voltage to the “IOVDD” pin on JP1
  5. Apply digital communication signals to header J4 on the EVM:
    1. Connect POCI (peripheral out, controller in) from the controller to the SDO pin
    2. Connect PICO (peripheral in, controller out) from the controller to the SDI pin
    3. Connect SCLK from the controller to the SCLK pin
    4. Connect CS from the controller to the CS pin
    5. Connect an I/O pin from the controller to the DRDY pin. DRDY is an output from the ADC that indicates when new data are ready to be clocked out of the ADC. Write a user-defined data collection routine that monitors this pin (polling or interrupt) and only transfers data after a falling edge
    6. (Optional) Connect I/O pins from the controller to the START and RESET pins to control conversions and reset the device, respectively
  6. (Optional) Connect an external Section 2.6 or Section 2.5
  7. Connect the signal source to the terminal blocks

Verify that the external power supply voltages, communication signal levels, and applied input signals meet the specifications listed in Table 1-1