SBAU361 December 2020
| Interface Mode | DCLKIN Multiplier (Serialization Factor) |
Example Sample Clock | Real Decimation Factor | Required DCLKIN Frequency |
|---|---|---|---|---|
| 2 Wire | 3.5 | 125 MSPS | 2 | 218.75 MHz |
| 1 Wire | 7 | 65 MSPS | 8 | 56.875 MHz |
| 1/2 Wire | 14 | 35 MSPS | 32 | 15.3125 MHz |
For this 14 bit, 2-Wire 8x Real Decimation example, apply a 125 MHz signal to J9 (sample clock) and a 54.6875 MHz signal to J7 (DCLKIN).
Apply a 5 MHz signal to J2 (ensure bandpass filter is used to reduce harmonics and noise of signal generator).
After launching the ADC35xx GUI perform the following steps:
Figure 4-5 ADC35XXEVM GUI: ADC3664EVM 8x Real
Decimation