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  1.   Abstract
  2.   Trademarks
  3. 1I2C Overview
    1. 1.1 History
    2. 1.2 I2C Speed Modes
  4. 2I2C Physical Layer
    1. 2.1 Two-Wire Communication
    2. 2.2 Open-Drain Connection
    3. 2.3 Non-Destructive Bus Contention
  5. 3I2C Protocol
    1. 3.1 I2C START and STOP
    2. 3.2 Logical Ones and Zeros
    3. 3.3 I2C Communication Frames
  6. 4I2C Examples
    1. 4.1 DAC80501 Example
      1. 4.1.1 DAC80501 DAC Data Register
      2. 4.1.2 DAC80501 I2C Example Write
    2. 4.2 ADS1115 Example
      1. 4.2.1 ADS1115 Configuration Register
      2. 4.2.2 ADS1115 I2C Example Read
      3. 4.2.3 ADS1115 Conversion Result
  7. 5Reserved Addresses
    1. 5.1 General Call
    2. 5.2 START Byte
    3. 5.3 C-Bus Address, Different Bus Format, Future Purposes
    4. 5.4 HS-Mode Controller Code
    5. 5.5 Device ID
    6. 5.6 10-Bit Target Addressing
      1. 5.6.1 10-Bit Target Addressing Write
      2. 5.6.2 10-Bit Target Addressing Read
  8. 6Advanced Topics
    1. 6.1 Clock Synchronization and Arbitration
    2. 6.2 Clock Stretching
    3. 6.3 Electrical Specifications
    4. 6.4 Voltage Level Translation
      1. 6.4.1 Example 1
      2. 6.4.2 Example 2
      3. 6.4.3 Example 3
      4. 6.4.4 Example 4
    5. 6.5 Pullup Resistor Sizing
      1. 6.5.1 Minimum Pullup Resistance Sizing
      2. 6.5.2 Maximum Pullup Resistance Sizing
  9. 7Protocols Similar to I2C
  10. 8Summary

6.5.2 Maximum Pullup Resistance Sizing

After the open-drain connection releases the output current, pullup resistors pull the bus connection high. The bus line output waveform has an exponential settling. As the resistor pulls the voltage up from ground, the voltage settling time is based on the bus capacitance (CB). The maximum pullup resistance is limited by the bus capacitance because of the I2C standard rise time specification. With a higher resistance, the pullup output rises too slowly, and does not reach the logical high fast enough.

Figure 6-14 Maximum Pullup Resistance Based on Rise from Pullup and Bus Capacitance

The equation for the exponential settling over time is shown in Equation 5 with the pullup resistance.

Equation 5. V(t) = (1 – e–t/RC ) × VCC

The rise time is based on the transition from the digital input low voltage (VIL) of 0.3 times the supply voltage to the digital input high voltage (VIH) of 0.7 times the supply voltage. The rise time is described in Table 6-3 while VIL and VIH are described in Table 6-4. The pullup settling with these parameters results in Equation 6 and Equation 7.

Equation 6. VIL = 0.3 × VCC = (1 – e–t1/RPCB ) × VCC
Equation 7. VIL = 0.7 × VCC = (1 – e–t2/RPCB ) × VCC

From the exponential settling equations, the rise time can be solved in terms of the maximum pullup resistance and the bus capacitance. In this example, the calculation is for a 400-pF bus capacitance (for the maximum bus capacitance) and supply voltage of 3.3 V. Equation 8 and Equation 9 solve for the rise time and then the maximum pullup resistance.

Equation 8. tRISE = t2 – t1 = 0.8473 × RP × CB
Equation 9. RP(max) = tRISE / (0.8473 × CB)

The rise time is dependent on the I2C mode. For this example, the standard mode can be used. Take the rise time of 1000 nanoseconds and divide by the quantity of 0.8473 times 400 pF. This gives a maximum resistance of 2.95 kΩ.

With a minimum resistance of 967 Ω and maximum resistance of 2.95 kΩ, these values appear to give a narrow range for the resistance. However, this small range is because the pullup resistor sizing is calculated to operate with the maximum standard-mode bus capacitance of 400 pF. This amount of bus capacitance is unusually large especially for a parasitic capacitance on the board. If the design has a lower bus capacitance (which is likely), the maximum resistance can be increased, reducing the power dissipated on the I2C bus.

For a more detailed description of I2C pullup resistor calculations see the I2C Bus Pullup Resistor Calculation application report. An I2C pullup calculator is also found in the Analog Engineer’s Calculator.