SBAA565 November   2022 ADC081C021 , ADC081C027 , ADC101C021 , ADC101C027 , ADC121C021 , ADC121C021-Q1 , ADC121C027 , ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1014 , ADS1015 , ADS1015-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1114 , ADS1115 , ADS1115-Q1 , ADS7823 , ADS7827 , ADS7828 , ADS7828-Q1 , ADS7830 , ADS7924 , AFE539A4 , DAC081C081 , DAC081C085 , DAC101C081 , DAC101C081Q , DAC101C085 , DAC121C081 , DAC121C085 , DAC43204 , DAC43401 , DAC43401-Q1 , DAC43608 , DAC43701 , DAC43701-Q1 , DAC53002 , DAC53004 , DAC53202 , DAC53204 , DAC53204W , DAC53401 , DAC53401-Q1 , DAC53608 , DAC53701 , DAC53701-Q1 , DAC5571 , DAC5573 , DAC5574 , DAC5578 , DAC60501 , DAC60502 , DAC63002 , DAC63004 , DAC63202 , DAC63204 , DAC6571 , DAC6573 , DAC6574 , DAC6578 , DAC70501 , DAC70502 , DAC7571 , DAC7573 , DAC7574 , DAC7578 , DAC7678 , DAC80501 , DAC80502 , DAC8571 , DAC8574

 

  1.   Abstract
  2.   Trademarks
  3. 1I2C Overview
    1. 1.1 History
    2. 1.2 I2C Speed Modes
  4. 2I2C Physical Layer
    1. 2.1 Two-Wire Communication
    2. 2.2 Open-Drain Connection
    3. 2.3 Non-Destructive Bus Contention
  5. 3I2C Protocol
    1. 3.1 I2C START and STOP
    2. 3.2 Logical Ones and Zeros
    3. 3.3 I2C Communication Frames
  6. 4I2C Examples
    1. 4.1 DAC80501 Example
      1. 4.1.1 DAC80501 DAC Data Register
      2. 4.1.2 DAC80501 I2C Example Write
    2. 4.2 ADS1115 Example
      1. 4.2.1 ADS1115 Configuration Register
      2. 4.2.2 ADS1115 I2C Example Read
      3. 4.2.3 ADS1115 Conversion Result
  7. 5Reserved Addresses
    1. 5.1 General Call
    2. 5.2 START Byte
    3. 5.3 C-Bus Address, Different Bus Format, Future Purposes
    4. 5.4 HS-Mode Controller Code
    5. 5.5 Device ID
    6. 5.6 10-Bit Target Addressing
      1. 5.6.1 10-Bit Target Addressing Write
      2. 5.6.2 10-Bit Target Addressing Read
  8. 6Advanced Topics
    1. 6.1 Clock Synchronization and Arbitration
    2. 6.2 Clock Stretching
    3. 6.3 Electrical Specifications
    4. 6.4 Voltage Level Translation
      1. 6.4.1 Example 1
      2. 6.4.2 Example 2
      3. 6.4.3 Example 3
      4. 6.4.4 Example 4
    5. 6.5 Pullup Resistor Sizing
      1. 6.5.1 Minimum Pullup Resistance Sizing
      2. 6.5.2 Maximum Pullup Resistance Sizing
  9. 7Protocols Similar to I2C
  10. 8Summary

6.5 Pullup Resistor Sizing

To design the system so that the bus speed is fast enough to meet the protocol bus speed, calculate the values for the pullup resistances.

With the open-drain connections of SDA and SCL, transitions from these lines from high to low and from low to high are dependent on the current sink from the device open-drain connection, the bus capacitance, and the pullup resistor value. Based on these different parameters, a minimum and maximum resistance can be calculated for the I2C bus speed.

Figure 6-12 Factors Affecting Pullup Resistor Sizing

The normal pullup resistor recommendation is 1 kΩ to 10 kΩ. With higher resistances, the I2C communication is slower. With lower resistances, the I2C communication requires more power. Based on the several different parameters, a minimum and maximum resistance can be calculated for the I2C bus speed.

Table 6-3 lists some of the parametric characteristics of the I2C bus. The table lists the bit rate of the I2C bus, the maximum rise time for the bus, and the maximum capacitive load on the bus. All of these parameters are used to determine the minimum and maximum pullup resistance values.

Table 6-3 Parametric Characteristics From I2C Protocol
Parameter Standard-mode (MAX) Fast-mode (MAX) Fast-mode Plus
(MAX)		 Unit
fSCL SCLK clock frequency 0 to 100 0 to 400 0 to 1000 kHz
tr Rise time of both SDA and SCL signals 1000 300 120 ns
Cb Capacitive load for each bus line 400 400 550 pF

In addition to these parameters, the I2C input and output voltage minimums and maximums are considered. Table 6-4 describes these voltages.

Table 6-4 Characteristics of SDA and SCL Input and Output Voltages
Parameter Standard Mode Fast Mode Fast Mode Plus Unit
MIN MAX MIN MAX MIN MAX
VIL Low-level input voltage –0.5 0.3 × VCC –0.5 0.3 × VCC –0.5 0.3 × VCC V
VIH High-level input voltage 0.7 × VCC VCC + 0.5 0.7 × VCC VCC + 0.5 0.7 × VCC VCC + 0.5 V
VOL Low-level output voltage, 3 mA sink current; VCC > 2 V 0 0.4 0 0.4 0 0.4 V
Low-level output voltage, 3 mA sink current; VCC ≤ 2 V - - 0 0.2 × VCC 0 0.2 × VCC V