ZHCSO02B July   2007  – July 2021 TRSF3221E

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Resistance Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, Driver
    8. 6.8  Switching Characteristics, Driver
    9. 6.9  Electrical Characteristics, Receiver
    10. 6.10 Switching Characteristics, Receiver
    11. 6.11 Electrical Characteristics, Auto-Powerdown
    12. 6.12 Switching Characteristics, Auto-Powerdown
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
      2. 9.1.2 Application Performance Plot
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.10 Switching Characteristics, Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 9-1)
PARAMETER TEST CONDITIONS(1) TYP(2) UNIT
tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 7-3

RGT package

 100 ns

DB or PW package

150
tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 7-3

RGT package

 125 ns

DB or PW package

150
ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tsk(p) Pulse skew(3) See Figure 7-3

RGT package

 25 ns

DB or PW package

50
(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.