ZHCSNG0A April 2023 – April 2024 TPS929160-Q1
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
Table 6-100 lists the memory-mapped registers for the CONF registers. All register offset addresses not listed in Table 6-100 should be considered as reserved locations and the register contents should not be modified.
Configuration Register
Offset | Acronym | Register Name | Section |
---|---|---|---|
70h | DIAGEN0 | OUTAn, OUTBn Diagnostics Enable Setting | Go |
71h | DIAGEN1 | OUTCn, OUTDn Diagnostics Enable Setting | Go |
72h | DIAGEN2 | OUTEn, OUTFn Diagnostics Enable Setting | Go |
73h | DIAGEN3 | OUTGn, OUTHn Diagnostics Enable Setting | Go |
74h | SLSTHSEL0 | OUTAn, OUTBn Single-LED Short Threshold Selecting | Go |
75h | SLSTHSEL1 | OUTCn, OUTDn Single-LED Short Threshold Selecting | Go |
76h | SLSTHSEL2 | OUTEn, OUTFn Single-LED Short Threshold Selecting | Go |
77h | SLSTHSEL3 | OUTGn, OUTHn Single-LED Short Threshold Selecting | Go |
78h | SLSDAC0 | Single-LED Short Threshold0 Setting | Go |
79h | SLSDAC1 | Single-LED Short Threshold1 Setting | Go |
7Ah | REFERENCE | Reference Setting | Go |
7Bh | DIAG | Diagnostics Setting | Go |
7Ch | DIAGMASK | Diagnostics Mask Setting | Go |
7Dh | OUTMASK | OUTXn Diagnostics Mask Setting | Go |
7Eh | DIM | Dimming Parameter Setting | Go |
7Fh | DIM-R | Reserved Register | Go |
80h | FSMAP0 | OUTAn, OUTBn Fail-safe Mapping Setting | Go |
81h | FSMAP1 | OUTCn, OUTDn Fail-safe Mapping Setting | Go |
82h | FSMAP2 | OUTEn, OUTFn Fail-safe Mapping Setting | Go |
83h | FSMAP3 | OUTGn, OUTHn Fail-safe Mapping Setting | Go |
84h | FLEXWIRE0 | FlewWire Parameter Setting | Go |
85h | FLEXWIRE1 | FlewWire Parameter Setting | Go |
86h | FLEXWIRE2 | FlewWire Parameter Setting | Go |
87h | CRC | EEPROM CRC | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-101 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DIAGEN0 is shown in Figure 6-98 and described in Table 6-102.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAGENOUTB1 | DIAGENOUTB0 | RESERVED | DIAGENOUTA1 | DIAGENOUTA0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DIAGENOUTB1 | R/W | X | Diagnostics enable register for OUTB1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
4 | DIAGENOUTB0 | R/W | X | Diagnostics enable register for OUTB0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
3-2 | RESERVED | R | 0h | Reserved |
1 | DIAGENOUTA1 | R/W | X | Diagnostics enable register for OUTA1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
0 | DIAGENOUTA0 | R/W | X | Diagnostics enable register for OUTA0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
DIAGEN1 is shown in Figure 6-99 and described in Table 6-103.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAGENOUTD1 | DIAGENOUTD0 | RESERVED | DIAGENOUTC1 | DIAGENOUTC0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DIAGENOUTD1 | R/W | X | Diagnostics enable register for OUTD1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
4 | DIAGENOUTD0 | R/W | X | Diagnostics enable register for OUTD0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
3-2 | RESERVED | R | 0h | Reserved |
1 | DIAGENOUTC1 | R/W | X | Diagnostics enable register for OUTC1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
0 | DIAGENOUTC0 | R/W | X | Diagnostics enable register for OUTC0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
DIAGEN2 is shown in Figure 6-100 and described in Table 6-104.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAGENOUTF1 | DIAGENOUTF0 | RESERVED | DIAGENOUTE1 | DIAGENOUTE0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DIAGENOUTF1 | R/W | X | Diagnostics enable register for OUTF1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
4 | DIAGENOUTF0 | R/W | X | Diagnostics enable register for OUTF0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
3-2 | RESERVED | R | 0h | Reserved |
1 | DIAGENOUTE1 | R/W | X | Diagnostics enable register for OUTE1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
0 | DIAGENOUTE0 | R/W | X | Diagnostics enable register for OUTE0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
DIAGEN3 is shown in Figure 6-101 and described in Table 6-105.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIAGENOUTH1 | DIAGENOUTH0 | RESERVED | DIAGENOUTG1 | DIAGENOUTG0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | DIAGENOUTH1 | R/W | X | Diagnostics enable register for OUTH1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
4 | DIAGENOUTH0 | R/W | X | Diagnostics enable register for OUTH0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
3-2 | RESERVED | R | 0h | Reserved |
1 | DIAGENOUTG1 | R/W | X | Diagnostics enable register for OUTG1 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
0 | DIAGENOUTG0 | R/W | X | Diagnostics enable register for OUTG0 Load EEPROM data when reset 0h = Disabled 1h = Enabled |
SLSTHSEL0 is shown in Figure 6-102 and described in Table 6-106.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLSTHOUTB1 | SLSTHOUTB0 | RESERVED | SLSTHOUTA1 | SLSTHOUTA0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | SLSTHOUTB1 | R/W | X | Single-LED short-circuit threshold selection register for OUTB1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
4 | SLSTHOUTB0 | R/W | X | Single-LED short-circuit threshold selection register for OUTB0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
3-2 | RESERVED | R | 0h | Reserved |
1 | SLSTHOUTA1 | R/W | X | Single-LED short-circuit threshold selection register for OUTA1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
0 | SLSTHOUTA0 | R/W | X | Single-LED short-circuit threshold selection register for OUTA0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
SLSTHSEL1 is shown in Figure 6-103 and described in Table 6-107.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLSTHOUTD1 | SLSTHOUTD0 | RESERVED | SLSTHOUTC1 | SLSTHOUTC0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | SLSTHOUTD1 | R/W | X | Single-LED short-circuit threshold selection register for OUTD1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
4 | SLSTHOUTD0 | R/W | X | Single-LED short-circuit threshold selection register for OUTD0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
3-2 | RESERVED | R | 0h | Reserved |
1 | SLSTHOUTC1 | R/W | X | Single-LED short-circuit threshold selection register for OUTC1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
0 | SLSTHOUTC0 | R/W | X | Single-LED short-circuit threshold selection register for OUTC0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
SLSTHSEL2 is shown in Figure 6-104 and described in Table 6-108.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLSTHOUTF1 | SLSTHOUTF0 | RESERVED | SLSTHOUTE1 | SLSTHOUTE0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | SLSTHOUTF1 | R/W | X | Single-LED short-circuit threshold selection register for OUTF1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
4 | SLSTHOUTF0 | R/W | X | Single-LED short-circuit threshold selection register for OUTF0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
3-2 | RESERVED | R | 0h | Reserved |
1 | SLSTHOUTE1 | R/W | X | Single-LED short-circuit threshold selection register for OUTE1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
0 | SLSTHOUTE0 | R/W | X | Single-LED short-circuit threshold selection register for OUTE0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
SLSTHSEL3 is shown in Figure 6-105 and described in Table 6-109.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLSTHOUTH1 | SLSTHOUTH0 | RESERVED | SLSTHOUTG1 | SLSTHOUTG0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | SLSTHOUTH1 | R/W | X | Single-LED short-circuit threshold selection register for OUTH1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
4 | SLSTHOUTH0 | R/W | X | Single-LED short-circuit threshold selection register for OUTH0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
3-2 | RESERVED | R | 0h | Reserved |
1 | SLSTHOUTG1 | R/W | X | Single-LED short-circuit threshold selection register for OUTG1 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
0 | SLSTHOUTG0 | R/W | X | Single-LED short-circuit threshold selection register for OUTG0 Load EEPROM data when reset 0h = SLSTH0 is selected 1h = SLSTH1 is selected |
SLSDAC0 is shown in Figure 6-106 and described in Table 6-110.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLSTH0 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SLSTH0 | R/W | X | Single-LED short-circuit setting register for SLSTH0 Load EEPROM data when reset V(SLSTH0) = SLSTH0*0.125V + 2.5V |
SLSDAC1 is shown in Figure 6-107 and described in Table 6-111.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLSTH1 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SLSTH1 | R/W | X | Single-LED short-circuit setting register for SLSTH1 Load EEPROM data when reset V(SLSTH1) = SLSTH1*0.125V + 2.5V |
REFERENCE is shown in Figure 6-108 and described in Table 6-112.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SLSEN | REFRANGE | LOWSUPTH | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SLSEN | R/W | X | Enable register for single-LED short-ciruit diagnostics Load EEPROM data when reset 0h = Disabled 1h = Enabled |
6-5 | REFRANGE | R/W | X | Reference current ratio setting register Load EEPROM data when reset 0h = 64 1h = 128 2h = 256 3h = 512 |
4-0 | LOWSUPTH | R/W | X | Supply low threshold setting register Load EEPROM data when reset V(LOWSUPTH) = LOWSUPTH*1V + 4V |
DIAG is shown in Figure 6-109 and described in Table 6-113.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IRETRY | BLANK | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IRETRY | R/W | X | LED open-circuit and short-circuit retry current setting register I(RETRY) = (IRETRY*4 + 4)/64*I(FULL_RANGE) Load EEPROM data when reset |
3-0 | BLANK | R/W | X | Diagnostics blank time setting register Load EEPROM data when reset 0h = 100µs 1h = 20µs 2h = 30µs 3h = 50µs 4h = 80µs 5h = 150µs 6h = 200µs 7h = 300µs 8h = 500µs 9h = 800µs Ah = 1ms Bh = 1.2ms Ch = 1.5ms Dh = 2ms Eh = 3ms Fh = 4ms |
DIAGMASK is shown in Figure 6-110 and described in Table 6-114.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASKLOWSUP | MASKSUPUV | MASKREF | MASKPRETSD | MASKTSD | MASKEEPCRC | RESERVED | |
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MASKLOWSUP | R/W | X | Supply low fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
6 | MASKSUPUV | R/W | X | Supply undervoltage fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
5 | MASKREF | R/W | X | REF pin fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
4 | MASKPRETSD | R/W | X | Thermal pre-warning fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
3 | MASKTSD | R/W | X | Thermal shutdown fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
2 | MASKEEPCRC | R/W | X | EEPROM CRC fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
1-0 | RESERVED | R | 0h | Reserved |
OUTMASK is shown in Figure 6-111 and described in Table 6-115.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MASKOPEN | MASKSHORT | MASKSLS | ||||
R-0h | R/W-X | R/W-X | R/W-X | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | Reserved |
2 | MASKOPEN | R/W | X | Output open-circuit fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
1 | MASKSHORT | R/W | X | Output short-circuit fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
0 | MASKSLS | R/W | X | Single-LED short-circuit fault mask register Load EEPROM data when reset 0h = Fault report is enabled 1h = Fault report is disabled |
DIM is shown in Figure 6-112 and described in Table 6-116.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXPEN | PSEN | 12BIT | PSMEN | PWMFREQ | |||
R/W-X | R/W-X | R/W-X | R/W-X | R/W-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EXPEN | R/W | X | Enable register for exponential dimming curve Load EEPROM data when reset 0h = Disabled 1h = Enabled |
6 | PSEN | R/W | X | Enable register for phase shift dimming Load EEPROM data when reset 0h = Disabled 1h = Enabled |
5 | 12BIT | R/W | X | Enable register for 12-bit dimming resolution diagnostics Load EEPROM data when reset 0h = Disabled 1h = Enabled |
4 | PSMEN | R/W | X | Enable register for digital power save mode Load EEPROM data when reset 0h = Disabled 1h = Enabled |
3-0 | PWMFREQ | R/W | X | PWM dimming frequency setting register Load EEPROM data when reset 0h = 200Hz 1h = 250Hz 2h = 300Hz 3h = 350Hz 4h = 400Hz 5h = 500Hz 6h = 600Hz 7h = 800Hz 8h = 1000Hz 9h = 1200Hz Ah = 2000Hz Bh = 4000Hz Ch = 5900Hz Dh = 7800Hz Eh = 9600Hz Fh = 20800Hz |
DIM-R is shown in Figure 6-113 and described in Table 6-117.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RESERVED | R | 0h | Reserved |
FSMAP0 is shown in Figure 6-114 and described in Table 6-118.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FSOUTB1 | FSOUTB0 | RESERVED | FSOUTA1 | FSOUTA0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | FSOUTB1 | R/W | X | Fail-safe state control input mapping for OUTB1 Load EEPROM data when reset 0h = OUTB1 is mapped to FS0 in fail-safe state 1h = OUTB1 is mapped to FS1 in fail-safe state |
4 | FSOUTB0 | R/W | X | Fail-safe state control input mapping for OUTB0 Load EEPROM data when reset 0h = OUTB0 is mapped to FS0 in fail-safe state 1h = OUTB0 is mapped to FS1 in fail-safe state |
3-2 | RESERVED | R | 0h | Reserved |
1 | FSOUTA1 | R/W | X | Fail-safe state control input mapping for OUTA1 Load EEPROM data when reset 0h = OUTA1 is mapped to FS0 in fail-safe state 1h = OUTA1 is mapped to FS1 in fail-safe state |
0 | FSOUTA0 | R/W | X | Fail-safe state control input mapping for OUTA0 Load EEPROM data when reset 0h = OUTA0 is mapped to FS0 in fail-safe state 1h = OUTA0 is mapped to FS1 in fail-safe state |
FSMAP1 is shown in Figure 6-115 and described in Table 6-119.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FSOUTD1 | FSOUTD0 | RESERVED | FSOUTC1 | FSOUTC0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | FSOUTD1 | R/W | X | Fail-safe state control input mapping for OUTD1 Load EEPROM data when reset 0h = OUTD1 is mapped to FS0 in fail-safe state 1h = OUTD1 is mapped to FS1 in fail-safe state |
4 | FSOUTD0 | R/W | X | Fail-safe state control input mapping for OUTC2 Load EEPROM data when reset 0h = OUTD0 is mapped to FS0 in fail-safe state 1h = OUTD0 is mapped to FS1 in fail-safe state |
3-2 | RESERVED | R | 0h | Reserved |
1 | FSOUTC1 | R/W | X | Fail-safe state control input mapping for OUTC1 Load EEPROM data when reset 0h = OUTC1 is mapped to FS0 in fail-safe state 1h = OUTC1 is mapped to FS1 in fail-safe state |
0 | FSOUTC0 | R/W | X | Fail-safe state control input mapping for OUTC0 Load EEPROM data when reset 0h = OUTC0 is mapped to FS0 in fail-safe state 1h = OUTC0 is mapped to FS1 in fail-safe state |
FSMAP2 is shown in Figure 6-116 and described in Table 6-120.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FSOUTF1 | FSOUTF0 | RESERVED | FSOUTE1 | FSOUTE0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | FSOUTF1 | R/W | X | Fail-safe state control input mapping for OUTF1 Load EEPROM data when reset 0h = OUTF1 is mapped to FS0 in fail-safe state 1h = OUTF1 is mapped to FS1 in fail-safe state |
4 | FSOUTF0 | R/W | X | Fail-safe state control input mapping for OUTF0 Load EEPROM data when reset 0h = OUTF0 is mapped to FS0 in fail-safe state 1h = OUTF0 is mapped to FS1 in fail-safe state |
3-2 | RESERVED | R | 0h | Reserved |
1 | FSOUTE1 | R/W | X | Fail-safe state control input mapping for OUTE1 Load EEPROM data when reset 0h = OUTE1 is mapped to FS0 in fail-safe state 1h = OUTE1 is mapped to FS1 in fail-safe state |
0 | FSOUTE0 | R/W | X | Fail-safe state control input mapping for OUTE0 Load EEPROM data when reset 0h = OUTE0 is mapped to FS0 in fail-safe state 1h = OUTE0 is mapped to FS1 in fail-safe state |
FSMAP3 is shown in Figure 6-117 and described in Table 6-121.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FSOUTH1 | FSOUTH0 | RESERVED | FSOUTG1 | FSOUTG0 | ||
R-0h | R/W-X | R/W-X | R-0h | R/W-X | R/W-X | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | Reserved |
5 | FSOUTH1 | R/W | X | Fail-safe state control input mapping for OUTH1 Load EEPROM data when reset 0h = OUTH1 is mapped to FS0 in fail-safe state 1h = OUTH1 is mapped to FS1 in fail-safe state |
4 | FSOUTH0 | R/W | X | Fail-safe state control input mapping for OUTH0 Load EEPROM data when reset 0h = OUTH0 is mapped to FS0 in fail-safe state 1h = OUTH0 is mapped to FS1 in fail-safe state |
3-2 | RESERVED | R | 0h | Reserved |
1 | FSOUTG1 | R/W | X | Fail-safe state control input mapping for OUTG1 Load EEPROM data when reset 0h = OUTG1 is mapped to FS0 in fail-safe state 1h = OUTG1 is mapped to FS1 in fail-safe state |
0 | FSOUTG0 | R/W | X | Fail-safe state control input mapping for OUTG0 Load EEPROM data when reset 0h = OUTG0 is mapped to FS0 in fail-safe state 1h = OUTG0 is mapped to FS1 in fail-safe state |
FLEXWIRE0 is shown in Figure 6-118 and described in Table 6-122.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDTIMER | DBWTIMER | ACKEN | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | WDTIMER | R/W | X | Communication watchdog timer setting register Load EEPROM data when reset 0h = Disabled, do not automatically enter fail-safe state 1h = 200µs 2h = 500µs 3h = 1ms 4h = 2ms 5h = 5ms 6h = 10ms 7h = 20ms 8h = 50ms 9h = 100ms Ah = 200ms Bh = 500ms Ch = 0µs, directly enter fail-safe state Dh = 0µs, directly enter fail-safe state Eh = 0µs, directly enter fail-safe state Fh = 0µs, directly enter fail-safe state |
3-1 | DBWTIMER | R/W | X | Data transaction break waiting timer setting register Load EEPROM data when reset 0h = 1ms 1h = 125µs 2h = 250µs 3h = 500µs 4h = 1.25ms 5h = 2.5ms 6h = 5ms 7h = 5ms |
0 | ACKEN | R/W | X | Enable register for acknowledgement Load EEPROM data when reset 0h = Disabled 1h = Enabled |
FLEXWIRE1 is shown in Figure 6-119 and described in Table 6-123.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTADDR | DEVADDR | |||||
R-0h | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | INTADDR | R/W | X | Devce address selection register Load EEPROM data when reset 0h = Device address set by ADDR2/ADDR1 and ADDR0 pins 1h = Device address set by DEVADDR |
3-0 | DEVADDR | R/W | X | Device address setting register Load EEPROM data when reset 0h = slave address is 0000b 1h = slave address is 0001b 2h = slave address is 0010b 3h = slave address is 0011b 4h = slave address is 0100b 5h = slave address is 0101b 6h = slave address is 0110b 7h = slave address is 0111b 8h = slave address is 1000b 9h = slave address is 1001b Ah = slave address is 1010b Bh = slave address is 1011b Ch = slave address is 1100b Dh = slave address is 1101b Eh = slave address is 1110b Fh = slave address is 1111b |
FLEXWIRE2 is shown in Figure 6-120 and described in Table 6-124.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OFAF | INITTIMER | |||||
R-0h | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R | 0h | Reserved |
4 | OFAF | R/W | X | Output one-fail-all-fail setting register in fail-safe state Load EEPROM data when reset 0h = OFAF Disabled 1h = OFAF Enabled |
3-0 | INITTIMER | R/W | X | Initialization timer setting register Load EEPROM data when reset 0h = 0ms 1h = 50ms 2h = 20ms 3h = 10ms 4h = 5ms 5h = 2ms 6h = 1ms 7h = 500µs 8h = 200µs 9h = 100µs Ah = 50µs Bh = 50µs Ch = 50µs Dh = 50µs Eh = 50µs Fh = 50µs |
CRC is shown in Figure 6-121 and described in Table 6-125.
Return to the Summary Table.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EEPCRC | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | EEPCRC | R/W | X | CRC reference for all EEPROM registers including RESERVED registers, manufacture default CRC result is 81h Load EEPROM data when reset |