ZHCSMK8A December   2020  – April 2021 TPS7B87-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good (PG)
      2. 7.3.2 Adjustable Power-Good Delay Timer (DELAY)
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Thermal Shutdown
      5. 7.3.5 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Functional Mode Comparison
      2. 7.4.2 Normal Operation
      3. 7.4.3 Dropout Operation
      4. 7.4.4 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Pulling Up the PG Pin to a Different Voltage
      7. 8.1.7 Power-Good
        1. 8.1.7.1 Setting the Adjustable Power-Good Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Package Mounting
      2. 10.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Thermal Performance Versus Copper Area

The most used thermal resistance parameter RθJA is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the Thermal Information table in the Section 6 section is determined by the JEDEC standard (see Figure 8-1), PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.

GUID-2BF2C0B9-4F00-41EC-AD78-3CA4192C654F-low.gifFigure 8-1 JEDEC Standard 2s2p PCB

Figure 8-2 through Figure 8-5 illustrate the functions of RθJA and ψJB versus copper area and thickness. These plots are generated with a 101.6-mm x 101.6-mm x 1.6-mm PCB of two and four layers. For the 4-layer board, inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 2x3 (DDA package) or a 3x4 (KVU package) array of thermal vias with a 300-µm drill diameter and 25-µm copper plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

GUID-20201130-CA0I-JXZ9-VQBB-ZLGZJQHRDMXL-low.gifFigure 8-2 RθJA vs Copper Area (DDA Package)
GUID-20201130-CA0I-KJZJ-CKKS-C4P8SCJXLBHP-low.gifFigure 8-4 RθJA vs Copper Area (KVU Package)
GUID-20201130-CA0I-VKGL-ZWR5-K0NZZNWKFNXK-low.gifFigure 8-3 ψJB vs Copper Area (DDA Package)
GUID-20201130-CA0I-23XD-VJ0L-KQLZR1BXC847-low.gifFigure 8-5 ψJB vs Copper Area (KVU Package)