ZHCSLB3B April   2020  – May 2025 TPS7B84-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Undervoltage Lockout
      3. 6.3.3 Thermal Shutdown
      4. 6.3.4 Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Selection
      2. 7.1.2 Adjustable Device Feedback Resistor Selection
      3. 7.1.3 Feed-Forward Capacitor (CFF)
      4. 7.1.4 Dropout Voltage
      5. 7.1.5 Reverse Current
      6. 7.1.6 Power Dissipation (PD)
        1. 7.1.6.1 Thermal Performance Versus Copper Area
        2. 7.1.6.2 Power Dissipation vs Ambient Temperature
      7. 7.1.7 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DCY|4
  • DRB|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance

As depicted in Figure 7-11 and Figure 7-12, place the input and output capacitors close to the device for the layout of the TPS7B84-Q1. In order to enhance the thermal performance, place as many vias as possible around the device. These vias improve the heat transfer between the different GND planes in the PCB.

To improve ac performance such as PSRR, output noise, and transient response, TI recommends a board design with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.

Minimize equivalent series inductance (ESL) and ESR in order to maximize performance and ensure stability. Place each capacitor as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI strongly discourages the use of vias and long traces to connect the capacitors because these can negatively impact system performance and may even cause instability.

If possible, and to ensure the maximum performance specified in this document, use the same layout pattern used for the TPS7B84-Q1 evaluation board, available at www.ti.com.