ZHCSQC5B December   2022  – February 2024 TPS7A21-Q1

PRODMIX  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Enable (EN)
      2. 6.3.2 Low Output Noise
      3. 6.3.3 Active Discharge
      4. 6.3.4 Dropout Voltage
      5. 6.3.5 Foldback Current Limit
      6. 6.3.6 Undervoltage Lockout
      7. 6.3.7 Thermal Overload Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Load Transient Response
      4. 7.1.4 Undervoltage Lockout (UVLO) Operation
      5. 7.1.5 Power Dissipation (PD)
      6. 7.1.6 Estimating Junction Temperature
      7. 7.1.7 Recommended Area For Continuous Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Power Dissipation and Device Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.5 Electrical Characteristics

specified over operating temperature range (TJ = –40℃ to +150℃), VIN = VOUT(NOM) + 0.3V or 2V, whichever is greater, VEN = 1.0V, IOUT = 1mA, CIN = 1µF, COUT = 1µF (unless otherwise noted); all typical values are at TJ = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ΔVOUT Output voltage tolerance VIN = (VOUT(NOM) + 0.3V) to 6.0V,
IOUT = 1mA to 500mA, 
VOUT ≥ 3.3V 		 –2.25 1.5 %
VIN = (VOUT(NOM) + 0.3 V) to 6.0V,
IOUT = 1mA to 500mA, 
2.8V ≤ VOUT < 3.3V 		 –2.5 1.5
VIN = (VOUT(NOM) + 0.3V) to 6.0V,
IOUT = 1mA 
VOUT ≥ 2.8V 		 –1 1
VIN = (VOUT(NOM) + 0.3V) to 6.0V,
IOUT = 1mA to 500mA, 
VOUT < 2.8V 		 –70 50 mV
VIN = (VOUT(NOM) + 0.3V) to 6.0V,
IOUT = 1mA
VOUT < 2.8V 		 –50 50
ΔVOUT Line regulation VIN = (VOUT(NOM) + 0.3V) to 6.0V,
IOUT = 1mA		 0.03 %/V
ΔVOUT Load regulation IOUT = 1mA to 500mA  0.003 %/mA
IGND Quiescent current VEN = VIN, VIN = 6.0V, IOUT = 0mA TJ = 25°C 6.5 9 µA
TJ = –40°C to 85°C 11
TJ = –40°C to 125°C 15
TJ = –40°C to 150°C 18
VEN = VIN, VIN = 6.0V, IOUT = 500mA 2300 3500
ISHTDWN Shutdown current VEN = 0V (disabled), VIN = 6.0V, TJ = 25°C 0.15 1 µA
VEN = 0V (disabled), VIN = 6.0V, TJ = –40°C to 150°C 10
IQ(DO) Quiescent current in dropout VIN ≤  VOUT(NOM), IOUT = 0mA 7 15 µA
VDO Dropout voltage IOUT = 500mA,
VOUT = 95% × VOUT(NOM) 		 0.8V ≤ VOUT < 1.0V (1) 825 mV
1.0V ≤ VOUT < 1.2V (1) 605
1.2V ≤ VOUT < 1.5V (1) 470
1.5V ≤ VOUT < 2.5V 355
2.5V ≤ VOUT ≤ 5.5V 265
ICL Output current limit VOUT = 0.9 × VOUT(NOM) 650 1060 1500 mA
ISC Short-circuit current limit VOUT = 0 V 325 mA
PSRR Power-supply rejection ratio IOUT = 20mA,
VIN = VOUT + 1.0 V		 f = 100Hz 90 dB
f = 1kHz 91
f = 10kHz 71
f = 100kHz 61
f = 1MHz 50
IOUT = 500mA,
VIN = VOUT + 1.0 V		 f = 100Hz 65
f = 1kHz 85
f = 10kHz 79
f = 100kHz 44
f = 1MHz 50
VN Output noise voltage BW = 10Hz to
100kHz,
VOUT = 2.8V		 IOUT = 500mA 7.7 µVRMS
IOUT = 1mA 10
RPULLDOWN Output automatic discharge pulldown resistance VIN = 2V, VEN < VIL (output disabled) 150 Ω
TSD Thermal shutdown rising TJ rising 165 °C
Thermal shutdown falling TJ falling 140
VEN(LOW) Low input threshold VIN = 2.0V to 6.0V,
VEN falling until the output is disabled		 0.3 V
VEN(HI) High input threshold VIN = 2.0V to 6.0V,
VEN rising until the output is enabled		 0.9 V
VUVLO UVLO threshold VIN rising 1.11 1.32 1.63 V
VIN falling 1.05 1.27 1.57
VUVLO(HYST) UVLO hysteresis 50 mV
IEN EN pin leakage current VEN = 6.0V and VIN = 6.0V 100 250 nA
REN(PULL-DOWN) Smart enable pulldown resistor 440 kΩ
tON Turnon time From VEN > VIH to VOUT = 95% of VOUT(NOM) 120 200 280 µs
(1) Dropout voltages for VOUT values below or very near the UVLO threshold are not measured directly. Values shown are verified by simulation.