ZHCSD04E November   2014  – March 2022 TPS65400

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Operational Parameters
    8. 7.8 Package Dissipation Ratings
    9. 7.9 Typical Characteristics: System Efficiency
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Startup Timing and Power Sequencing
        1. 8.3.1.1 Startup Timing
        2. 8.3.1.2 External Sequencing
        3. 8.3.1.3 Internal Sequencing
      2. 8.3.2  UVLO and Precision Enables
      3. 8.3.3  Soft-Start and Prebiased Startup
        1. 8.3.3.1 Analog Soft-Start (Default) and Digital Soft-Start
        2. 8.3.3.2 Soft-Start Capacitor Selection
      4. 8.3.4  PWM Switching Frequency Selection
      5. 8.3.5  Clock Synchronization
      6. 8.3.6  Phase Interleaving
      7. 8.3.7  Fault Handling
      8. 8.3.8  OCP for SW1 to SW4
      9. 8.3.9  Overcurrent Protection for SW1 to SW4 in Current Sharing Operation
      10. 8.3.10 Recovery on Power Loss
      11. 8.3.11 Feedback Compensation
      12. 8.3.12 Adjusting Output Voltage
      13. 8.3.13 Digital Interface – PMBus
      14. 8.3.14 Initial Configuration
    4. 8.4 Device Functional Modes
      1. 8.4.1 CCM Operation Mode
      2. 8.4.2 CCM/DCM Operation Mode
      3. 8.4.3 Current Sharing Mode
    5. 8.5 Programming
      1. 8.5.1 PMBus
        1. 8.5.1.1 Overview
        2. 8.5.1.2 PMBus Protocol
          1. 8.5.1.2.1  PMBus Protocol
          2. 8.5.1.2.2  Transactions (No PEC)
          3. 8.5.1.2.3  Addressing
          4. 8.5.1.2.4  Startup
          5. 8.5.1.2.5  Bus Speed
          6. 8.5.1.2.6  I2CALERT Terminal
          7. 8.5.1.2.7  CONTROL Terminal
          8. 8.5.1.2.8  Packet Error Checking
          9. 8.5.1.2.9  Group Commands
          10. 8.5.1.2.10 Unsupported Features
      2. 8.5.2 PMBus Register Descriptions
        1. 8.5.2.1 Overview
        2. 8.5.2.2 Memory Model
        3. 8.5.2.3 Data Formats
        4. 8.5.2.4 Fault Monitoring
    6. 8.6 Register Maps
      1. 8.6.1 PMBus Core Commands
        1. 8.6.1.1  (00h) PAGE
        2. 8.6.1.2  (01h) OPERATION
        3. 8.6.1.3  (03h) CLEAR_FAULTS
        4. 8.6.1.4  (10h) WRITE_PROTECT
        5. 8.6.1.5  (11h) STORE_DEFAULT_ALL
        6. 8.6.1.6  (19h) CAPABILITY
        7. 8.6.1.7  (78h) STATUS_BYTE
        8. 8.6.1.8  (79h) STATUS_WORD
        9. 8.6.1.9  (7Ah) STATUS_VOUT
        10. 8.6.1.10 (80h) STATUS_MFR_SPECIFIC
        11. 8.6.1.11 (98h) PMBUS_REVISION
        12. 8.6.1.12 (ADh) IC_DEVICE_ID
        13. 8.6.1.13 (AEh) IC_DEVICE_REV
      2. 8.6.2 Manufacturer-Specific Commands
        1. 8.6.2.1  (D0h) USER_DATA_BYTE_00
        2. 8.6.2.2  (D1h) USER_DATA_BYTE_01
        3. 8.6.2.3  (D2h) PIN_CONFIG_00
        4. 8.6.2.4  (D3h) PIN_CONFIG_01
        5. 8.6.2.5  (D4h) SEQUENCE_CONFIG
        6. 8.6.2.6  (D5h) SEQUENCE_ORDER
        7. 8.6.2.7  (D6h) IOUT_MODE
        8. 8.6.2.8  (D7h) FREQUENCY_PHASE
        9. 8.6.2.9  (D8h) VREF_COMMAND
        10. 8.6.2.10 (D9h) IOUT_MAX
        11. 8.6.2.11 (DAh) USER_RAM_00
        12. 8.6.2.12 (DBh) SOFT_RESET
        13. 8.6.2.13 (DCh) RESET_DELAY
        14. 8.6.2.14 (DDh) TON_TOFF_DELAY
        15. 8.6.2.15 (DEh) TON_TRANSITION_RATE
        16. 8.6.2.16 (DFh) VREF_TRANSITION_RATE
        17. 8.6.2.17 (F0h) SLOPE_COMPENSATION
        18. 8.6.2.18 (F1h) ISENSE_GAIN
        19. 8.6.2.19 (FCh) DEVICE_CODE
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Internal Operation Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Component Selection
            1. 9.2.1.2.1.1 Output Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor Selection
          2. 9.2.1.2.2 Internal Operation With Some Switchers Disabled
          3. 9.2.1.2.3 Internal Operation With All Switchers Enabled
          4. 9.2.1.2.4 Example Configuration
          5. 9.2.1.2.5 Unused Switchers
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Current Sharing Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Current Sharing Timing Example
      3. 9.2.3 External Sequencing Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 External Sequencing Through PG Pins
          2. 9.2.3.2.2 External Sequencing Through SW
          3. 9.2.3.2.3 Example Configuration
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Related Parts
    2. 12.2 接收文档更新通知
    3. 12.3 术语表
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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8.6 Register Maps

Table 8-6 lists the PMBus commands. Commands 00h through CFh are defined in the PMBus Specification and are considered to be core commands that are standardized for all manufacturers and products. Commands D0h through FEh are manufacturer-specific and may be unique for each manufacturer and product. Commands that are not supported by the device are not listed.

Table 8-6 Supported PMBus Commands
CODENAMESMBUS TRANSACTION TYPE: WRITING DATASMBUS TRANSACTION TYPE: READING DATADATA BYTESPAGE SUPPORTSAVED TO DATA FLASHDESCRIPTION
00hPAGEWrite byteRead byte1—NoSelects output rail (see (00h) PAGE)
01hOPERATIONWrite byteRead byte100-03, FFNoStarts or stops output (see (01h) OPERATION)
03hCLEAR_FAULTSSend byte—000-03, FF—Clears all faults (see (03h) CLEAR_FAULTS)
10hWRITE_PROTECTWrite byteRead byte1—NoUsed to lock bus writes (see (10h) WRITE_PROTECT)
11hSTORE_DEFAULT_ALLSend byte—0——Stores operating memory to default store (see (11h) STORE_DEFAULT_ALL)
19hCAPABILITY—Read byte1——Describes PMBUS capabilities (see (19h) CAPABILITY)
78hSTATUS_BYTE—Read byte100-03, FF—Fault register (see (78h) STATUS_BYTE)
79hSTATUS_WORD—Read word200-03, FF—Fault register (see (79h) STATUS_WORD)
7AhSTATUS_VOUT—Read byte100-03, FF—Output fault register (see (7Ah) STATUS_VOUT)
80hSTATUS_MFR_SPECIFIC—Read byte1——Status register (PGOOD#_N) (see (80h) STATUS_MFR_SPECIFIC)
98hPMBUS_REVISION—Read byte1——PMBUS revision support (see (98h) PMBUS_REVISION)
ADhIC_DEVICE_ID—Read block7——IC part number in ASCII (see (ADh) IC_DEVICE_ID)
AEhIC_DEVICE_REV—Read block2——IC part revision code (see (AEh) IC_DEVICE_REV)
D0hUSER_DATA_BYTE_00Write byteRead byte1—YesUser-defined data (see (D0h) USER_DATA_BYTE_00)
D1hUSER_DATA_BYTE_01Write byteRead byte1—YesUser-defined data (see (D1h) USER_DATA_BYTE_01)
D2hPIN_CONFIG_00Write byteRead byte1—YesConfigures pin behavior (see (D2h) PIN_CONFIG_00)
D3hPIN_CONFIG_01Write byteRead byte100-03YesConfigures rail-specific pin behavior (see (D3h) PIN_CONFIG_01)
D4hSEQUENCE_CONFIGWrite byteRead byte1—YesConfigures sequence behavior (see (D4h) SEQUENCE_CONFIG)
D5hSEQUENCE_ORDERWrite byteRead byte100-03YesConfigures sequence order (see (D5h) SEQUENCE_ORDER)
D6hIOUT_MODEWrite byteRead byte100-03YesSets CCM / DCM, current sharing status (see (D6h) IOUT_MODE)
D7hFREQUENCY_PHASEWrite byteRead byte100-03YesSets switcher frequency and phase (see (D7h) FREQUENCY_PHASE)
D8hVREF_COMMANDWrite byteRead byte100-03YesSets reference voltage (VREF) (see (D8h) VREF_COMMAND)
D9hIOUT_MAXWrite byteRead byte100-03YesSets current limit (see (D9h) IOUT_MAX)
DAhUSER_RAM_00Write byteRead byte1—NoRESET notification (see (DAh) USER_RAM_00)
DBhSOFT_RESETSend byte—0——Soft resets device (see (DBh) SOFT_RESET)
DChRESET_DELAYWrite byteRead byte1—YesSets delay after reset (see (DCh) RESET_DELAY)
DDhTON_TOFF_DELAYWrite byteRead byte100-03YesSets delay before output begins to turn ON/OFF (see (DDh) TON_TOFF_DELAY)
DEhTON_TRANSITION_RATEWrite byteRead byte100-03YesSets soft-start time (see (DEh) TON_TRANSITION_RATE)
DFhVREF_TRANSITION_RATEWrite byteRead byte100-03YesSets ramping parameters for real-time Vref settings in output (see (DFh) VREF_TRANSITION_RATE)
E0h to EFh——————Reserved
F0hSLOPE_COMPENSATIONWrite byteRead byte100-03YesAdjusts control loop compensation (see (F0h) SLOPE_COMPENSATION)
F1hISENSE_GAINWrite byteRead byte100-03YesAdjusts control loop current sense (see (F1h) ISENSE_GAIN)
FChDEVICE_CODE—Read word2——IC part revision code (see (FCh) DEVICE_CODE)
Table 8-7 Command Bit-Mapping
CODENAMEDEFAULT VALUEBYTEBITS
7 (MSB)6543210 (LSB)
00hPAGE0xFF0PAGE
01hOPERATION0x800OPERATIONxxxx
03hCLEAR_FAULTS—
10hWRITE_PROTECT0x400WRITE_PROTECT
11hSTORE_DEFAULT_ALL—
19hCAPABILITY0xA00PECBUSSMB_ALERTxxxx
78hSTATUS_BYTE0b0XXXX0XX0xOFFVOUT_OVIOUT_OCTEMPERATURExCMLNONE OF THE ABOVE
79hSTATUS_WORD0b0XXXX0XX0xOFFVOUT_OVIOUT_OCTEMPERATURExCMLNONE OF THE ABOVE
0bX00XX0001VOUTxxMFRPOWER_GOOD_Nxxx
7AhSTATUS_VOUT0bX00X00000VOUT_OVxxVOUT_UVxxxx
80hSTATUS_MFR_
SPECIFIC		0b0000XXXX1xxxxPOWER_GOOD4_NPOWER_GOOD3_NPOWER_GOOD2_NPOWER_GOOD1_N
98hPMBUS_REVISION0x220Part I RevisionPart II Revision
ADhIC_DEVICE_ID0x070Length
0x4C1‘L’
0x4D2‘M’
0x323‘2’
0x364‘6’
0x345‘4’
0x336‘3’
0x307‘0’
AEhIC_DEVICE_REV0x020Length
0xFX1DEVICE_CODE_IDDEVICE_CODE_REV
0x002DEVICE_CODE_ID
D0hUSER_DATA_BYTE_000x000USER_DATA_BYTE_00
D1hUSER_DATA_BYTE_010x000USER_DATA_BYTE_01
D2hPIN_CONFIG_000x3C0xPGOOD_PIN_CONFIGENABLE_PIN_CONFIG
D3hPIN_CONFIG_010x000xxxxxxxSSPG_PIN_
CONFIG
D4hSEQUENCE_CONFIG0x000xxxxxxxSTART_PGOOD
D5hSEQUENCE_ORDER0x000xxxxSTOP_ORDERSTART_ORDER
D6hIOUT_MODE0b000000X10xxxxxxIOUT_SHARECCM
D7hFREQUENCY_PHASEPAGEVal0xPHASE_DELAYCLK_DIV
0x000x00
0x010x08
0x020x04
0x030x0C
D8hVREF_COMMAND0x140xVREF_COMMAND
D9hIOUT_MAXPAGEVal0xxxxxIOUT_MAX
0x000x04
0x010x04
0x020x03
0x030x03
DAhUSER_RAM_000x000xxxxxxxUSER_RAM_00
DBhSOFT_RESET—
DChRESET_DELAY0x000xxxxxRESET_DELAY
DDhTON_TOFF_DELAY0x010xxTON_DELAYTOFF_DELAY
DEhTON_TRANSITION_
RATE		0x020xxxxxxTON_RAMP_RATE
DFhVREF_TRANSITION_
RATE		0x980VREF_RAMP_
ENABLE		xVREF_RAMP_TIMESTEPVREF_RAMP_BITSTEP
F0hSLOPE_
COMPENSATION		0x010xxxxxxSLOPE_
COMPENSATION
F1hISENSE_GAIN0x010xxxxxxISENSE_GAIN
FChDEVICE_CODE0xFX0DEVICE_CODE_IDDEVICE_CODE_REV
0x001DEVICE_CODE_ID