This pin can be configured as an alternative MODE pin (in case MODE/STBY is configured for STBY-function) or as a RESET pin. The configuration of the pin is selected by MODE_RESET_CONFIG in MFP_2_CONFIG register. The polarity of this pin can be configured by writing to MODE_RESET_POLARITY in MFP_1_CONFIG register. The polarity-configuration must not change after power-up. Only MODE/RESET or MODE/STBY must be configured as MODE. If both are configured as MODE, MODE/RESET takes priority and MODE/STBY is ignored.

MODE/RESET configured as 'MODE':

• If configured as 'MODE', the pin-status determines the switching-mode of the buck-converters.
• Forcing this pin for longer than t_{DEGLITCH_MFP} forces the buck-regulators into PWM-mode (irrespective of load current). De-asserting this pin low allows the buck regulators to enter PFM-mode. The entry into PFM and exit from PFM is governed by the load current. Only one pin, either MODE/STBY or MODE/RESET must be configured as 'MODE'.
• The selection of auto-PFM/forced-PWM can also be controlled by writing to the bit MODE_I2C_CTRL in MFP_1_CONFIG register.
• A change of the MODE does not cause a state-transition.
• During power-up of any one of the three bucks, a MODE-change is blanked on this rail and only takes effect after the ramp completed.

MODE/RESET configured as 'RESET':

• In RESET configuration, this pin is edge sensitive, but still applies the deglitch time. Consequently, toggling this pin and holding the pin for longer than t_{DEGLITCH_RESET} causes a reset.
• By default, RESET is deasserted and RESET requests, via pin or I2C, are only serviced if the device is in ACTIVE state, STBY state, or transitions between these 2 states.
• The TPS6521905 supports WARM or COLD reset. The configuration is made by bit WARM_COLD_RESET_CONFIG in MFP_2_CONFIG register.
  • If configured for COLD reset, the device executes the power down sequence and transitions to INITIALIZE state. Then, EEPROM is reloaded and rails power-up again in normal power-up-sequence, provided there are no faults and no OFF-request. The execution of a COLD-reset sets the bit COLD_RESET_ISSUED in POWER_UP_STATUS_REG register. The read-out of this bit allows to track if a COLD-reset was performed. The bit gets set regardless if the reset was commanded by I2C or by the pin. The nINT-pin does not toggle based on this bit. Write W1C to clear the bit.
  • If configured for WARM reset, all enabled rails remain on, but the output voltage of rails that support dynamic voltage change is reset to the boot-voltage. Specifically, following configurations get reset to their boot-value: BUCK1_VSET, BUCK2_VSET, BUCK3_VSET, LDO1_VSET, LDO2_VSET, LDO1_BYP_CONFIG, LDO2_BYP_CONFIG and VSEL_SD_I2C_CTRL.

    All other bits, even in the same register, remain at their current state. For example, LDOx_LSW_CONFIG, BUCKx_BW_SEL, BUCKx_UV_THR_SEL and the MFP_1_CONFIG register bits do NOT get reset during a WARM-reset.

    WARM Reset cannot override the VSEL_SD-pin command. In other words: even if a WARM Reset occurs, if the VSEL_SD pin is commanding 1.8V-LDO mode, that remain in effect.

• A reset can also be triggered by writing to the bit WARM_RESET_I2C_CTRL respectively the bit COLD_RESET_I2C_CTRL in MFP_CTRL register.

Please see below truth-table for pin- and I2C-commands.

The * for MODE indicates that the MODE/RESET pin takes priority in case both, MODE/RESET and MODE/STBY are configured as 'MODE', and thus the respective pin to be observed is MODE/RESET.