ZHCSTA1 September   2023 TPS6521905-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 修订历史记录
  6. 5 引脚配置和功能
  7. 6 规格
    1. 6.1  绝对最大额定值
    2. 6.2  ESD 等级
    3. 6.3  建议运行条件
    4. 6.4  热性能信息
    5. 6.5  系统控制阈值
    6. 6.6  BUCK1 转换器
    7. 6.7  BUCK2、BUCK3 转换器
    8. 6.8  通用 LDO（LDO1、LDO2）
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIO 和多功能引脚（EN/PB/VSENSE、nRSTOUT、nINT、GPO1、GPO2、GPIO、MODE/RESET、MODE/STBY、VSEL_SD/VSEL_DDR）
    11. 6.11 电压和温度监测器
    12. 6.12 I2C 接口
    13. 6.13 典型特性
  8. 7 详细说明
    1. 7.1 概述
    2. 7.2 功能方框图
    3. 7.3 特性说明
      1. 7.3.1  上电时序
      2. 7.3.2  断电时序
      3. 7.3.3  按钮和使能输入 (EN/PB/VSENSE)
      4. 7.3.4  复位到 SoC (nRSTOUT)
      5. 7.3.5  降压转换器（Buck1、Buck2 和 Buck3）
        1. 7.3.5.1 双随机展频 (DRSS)
      6. 7.3.6  线性稳压器（LDO1 至 LDO4）
      7. 7.3.7  中断引脚 (nINT)
      8. 7.3.8  PWM/PFM 和低功耗模式 (MODE/STBY)
      9. 7.3.9  PWM/PFM 和复位 (MODE/RESET)
      10. 7.3.10 电压选择引脚 (VSEL_SD/VSEL_DDR)
      11. 7.3.11 通用输入或输出（GPO1、GPO2 和 GPIO）
      12. 7.3.12 与 I2C 兼容的接口
        1. 7.3.12.1 数据有效性
        2. 7.3.12.2 启动和停止条件
        3. 7.3.12.3 传输数据
    4. 7.4 器件功能模式
      1. 7.4.1 运行模式
        1. 7.4.1.1 OFF 状态
        2. 7.4.1.2 INITIALIZE 状态
        3. 7.4.1.3 活动状态
        4. 7.4.1.4 STBY 状态
        5. 7.4.1.5 故障处理
    5. 7.5 多 PMIC 运行
    6. 7.6 NVM 编程
      1. 7.6.1 TPS6521905-Q1 默认 NVM 设置
      2. 7.6.2 初始化状态下的 NVM 编程
      3. 7.6.3 运行状态下的 NVM 编程
    7. 7.7 用户寄存器
    8. 7.8 器件寄存器
  9. 8 应用和实施
    1. 8.1 应用信息
    2. 8.2 典型应用
      1. 8.2.1 典型应用示例
      2. 8.2.2 设计要求
      3. 8.2.3 详细设计过程
        1. 8.2.3.1 Buck1、Buck2、Buck3 设计过程
        2. 8.2.3.2 LDO1、LDO2 设计过程
        3. 8.2.3.3 LDO3、LDO4 设计过程
        4. 8.2.3.4 VSYS、VDD1P8
        5. 8.2.3.5 数字信号设计过程
      4. 8.2.4 应用曲线
    3. 8.3 电源相关建议
    4. 8.4 布局
      1. 8.4.1 布局指南
      2. 8.4.2 布局示例
  10. 9 器件和文档支持
    1. 9.1 文档支持
      1. 9.1.1 相关文档
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.9 General Purpose LDOs (LDO3, LDO4)

over operating free-air temperature range (unless otherwise noted)
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics
8.1.1 VIN Input Voltage (LDO-mode) (1) LDO-mode, maximum VVSYS 2.2 5.5 V
8.1.2 VIN Input Voltage (LSW-mode) (1) LSW-mode, maximum VVSYS 2.2 5.5 V
8.1.3 VOUT
LDO Output Voltage configurable Range

 VIN = 2.2V to 5.5V, maximum VVSYS 1.2 3.3 V
8.1.4 VOUT_STEP Output voltage Steps 1.2V ≤ VOUT ≤ 3.3V 50 mV
8.1.5 VDROPOUT Dropout Voltage VINmin ≤ VIN ≤ VIN, IOUT = IOUTmax 150 300 mV
8.1.6 VOUT_DC_ACCURACY Total DC accuracy including DC load and line regulation for all valid output voltages LDO-mode, VIN - VOUT > 300 mV –1% 1%
8.1.7 RBYPASS Bypass resistance in LSW-mode VIN = 3.3V, IOUT = 100mA, Loadswitch-mode enabled 1 Ω
8.2.1 VLOAD_TRANSIENT Transient load regulation, ΔVOUT VIN = 3.3V, VOUT = 1.80V, IOUT = 20% of IOUT_MAX to 80% of IOUT_MAX in 1µs, COUT = 2.2µF –25 25 mV
8.2.2 VLINE_TRANSIENT Transient line regulation,
ΔVOUT / VOUT		 On mode, not under dropout condition, VIN step = 600 mVPP, tr = tf = 10µs –25 25 mV
8.2.3 NOISERMS RMS Noise LDO-mode, f=100Hz to 100KHz, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 15 µVRMS
8.2.4 PSRR1KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 71 db
8.2.5 PSRR10KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 64 db
8.2.6 PSRR100KHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 61 db
8.2.7 PSRR1MHZ Power Supply Ripple Rejection LDO-mode, VIN = 3.3V, VOUT = 1.8V, IOUT = 300mA 26 db
8.3.1 IOUT Output Current 300 mA
8.3.2 ICURRENT_LIMIT Short Circuit Current Limit VIN = 3.6V, VOUT = 0V, Tested under a pulsed load condition 400 900 mA
8.3.3 IIN_RUSH LDO inrush current LDO- or LSW-mode, VIN = 3.3V and then LDO is enabled, COUT = 4µF, IOUT = 0 mA or 300mA 650 mA
8.3.4 RDISCHARGE Active only when converter is disabled 120 250 400 Ω
8.3.5a IQ_ACTIVE Quiescent Current in ACTIVE state at 25°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = 25°C		 25 30 µA
8.3.5b IQ_ACTIVE Quiescent Current in ACTIVE state -40°C to 125°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LDO-mode,
TJ = -40°C to 125°C		 25 40 µA
8.3.5b IQ_ACTIVE
Quiescent Current in ACTIVE state -40°C to 150°C
 		 VVSYS = VIN = 3.3 V, IOUT = 0 mA,
Applies to LDO-mode,
TJ = -40°C to 150°C		 25 40 µA
8.3.5c IQ_ACTIVE Quiescent Current in ACTIVE state at 25°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = 25°C		 60 112 µA
8.3.5d IQ_ACTIVE Quiescent Current in ACTIVE state -40°C to 125°C VVSYS = VIN = 3.3 V, IOUT = 0 mA
Applies to LSW-mode,
TJ = -40°C to 125°C		 70 145 µA
8.3.5d IQ_ACTIVE
Quiescent Current in ACTIVE state -40°C to 150°C
 		 VVSYS = VIN = 3.3 V, IOUT = 0 mA,
Applies to LSW-mode,
TJ = -40°C to 150°C		 70 145 µA
8.4.1 CIN Input Filtering Capacitance (2) 2.2 4.7 µF
8.4.2 COUT Output Filtering Capacitance (2) Connected from VLDOx to GND, LDO-mode 1.6 2.2 4 µF
8.4.3a COUT_TOTAL_FAST Total Capacitance at Output (Local + POL), fast ramp-time (3) 1 MHz < f < 10 MHz, impedance between output and point-of-load maximum 6nH 15 µF
8.4.3b COUT_TOTAL_SLOW Total Capacitance at Output (Local + POL), slow ramp-time (3) 1 MHz < f < 10 MHz, impedance between output and point-of-load maximum 6nH 30 µF
8.4.4 CESR Filtering capacitor ESR max 1MHz to 10MHz 10 20 mΩ
Timing Requirements
8.5.1a tRAMP_FAST Ramp Time fast Measured from enable to 98% of target value, LDO-mode, measured when enabled individually, assuming no residual voltage 660 µs
8.5.1b tRAMP_SLOW Ramp Time slow Measured from enable to 98% of target value, LDO-mode, measured when enabled individually, assuming no residual voltage 2.3 ms
8.5.2a tRAMP_SLEW_FAST Ramp Up Slew Rate fast LDO- or LSW-mode, measured from 0.5V to target value 25 mV/µs
8.5.2b tRAMP_SLEW_SLOW Ramp Up Slew Rate slow LDO- or LSW-mode, measured from 0.5V to target value 9 mV/µs
(1) PVIN_LDOx must not exceed VSYS
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.
(3) Additional capacitance, including local and POL, beyond the specified value can cause the LDO to become unstable