SLVSHR0 May   2025 TPS2HCS08-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 A Version Package
    2. 5.2 Pinout - Version A
    3. 5.3 Version B Package
    4. 5.4 Pinout - Version B
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Device Functional Modes
      1. 8.3.1 State Diagram
      2. 8.3.2 Output Control
      3. 8.3.3 SPI Mode Operation
      4. 8.3.4 Fault Reporting
      5. 8.3.5 SLEEP
      6. 8.3.6 CONFIG/ACTIVE
      7. 8.3.7 LIMP_HOME State (Version A only)
      8. 8.3.8 Battery Supply Input (VBB) Under-voltage
      9. 8.3.9 LOW POWER MODE (LPM) States
        1. 8.3.9.1 MANUAL_LPM State
        2. 8.3.9.2 AUTO_LPM State
    4. 8.4 Feature Description
      1. 8.4.1 Protection Mechanisms
        1. 8.4.1.1 Overcurrent Protection
          1. 8.4.1.1.1 Inrush Period - Overcurrent Protection
          2. 8.4.1.1.2 Overcurrent Protection - Steady State Operation
          3. 8.4.1.1.3 Programmable Fuse Protection
          4. 8.4.1.1.4 Immediate Shutdown Overcurrent Protection (IOCP)
          5. 8.4.1.1.5 Auto Retry and Latch-off Behavior
        2. 8.4.1.2 Thermal Shutdown
        3. 8.4.1.3 Reverse Battery
      2. 8.4.2 Diagnostic Mechanisms
        1. 8.4.2.1 Integrated ADC
        2. 8.4.2.2 Digital Current Sense Output
        3. 8.4.2.3 Output Voltage Measurement
        4. 8.4.2.4 MOSFET Temperature Measurement
        5. 8.4.2.5 Drain-to-Source Voltage (VDS) Measurement
        6. 8.4.2.6 VBB Voltage Measurement
        7. 8.4.2.7 VOUT Short-to-Battery and Open-Load
          1. 8.4.2.7.1 Measurement With Channel Output (FET) Enabled
          2. 8.4.2.7.2 Detection With Channel Output Disabled
    5. 8.5 Parallel Mode Operation
    6. 8.6 TPS2HCS08 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Thermal Considerations
        2. 9.2.2.2 Configuring the Capacitive Charging Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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6.6 SPI Timing Requirements

Over operating junction temperature TJ = –40°C to 150°C, VDD = 3.0V to 5.5V (measured with respect to the GND pin of the device)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ƒSPI SPI clock (SCLK) frequency CSDO = 30 pF, IO protection resistor 0.22 kΩ 8 MHz
thigh High time: SCLK logic high-time duration 45 ns
tlow Low time: SCLK logic low-time duration 45 ns
tsucs CS setup time: time delay between falling edge of CS and rising edge of SCLK 45 ns
tsu_SDI SDI setup time: setup time of SDI before the falling edge of SCLK 15 ns
th_SDI SDI hold time: hold time of SDI before the falling edge of SCLK 30 ns
td_SDO Delay time: time delay from rising edge of SCLK to data valid at SDO 30 ns
thcs Hold time: time between the falling edge of SCLK and rising edge of CS 45 ns
tdis_cs CS disable time, CS high to SDO high impedance 10 ns
thics SPI transfer inactive time (time between two transfers) during which CS must remain high 500 ns