The device includes a battery supply (VBB) under-voltage monitoring and a VDD under-voltage monitoring. Some of the internal reference and regulators and the output FETs are turned OFF when the VBB supply falls below the V_{BB_UVLOF} threshold. When the input VBB supply is lost, the device relies on the VDD supply input to keep the digital functions and registers alive. The SPI communication is also available as long as the VDD input is greater than V_{DD_UVLOF}. The VBB_UVLO fault and the VDD_UVLO bits can be read over SPI from the GLOBAL_FAULT_TYPE register. The VBB_UVLO and VDD_UVLO fault bits are latched if there is a fault for either and are cleared on read if the UVLO condition no longer exists. The following table indicates the device operation under a loss of supply condition.

The register information may be lost when both the VBB and VDD supplies are below the POR and UVLO conditions respectively. The device is able to indicate with a register read of the POR bit in the GLOBAL_FAULT_TYPE register that a reset of the digital has occurred. This will ensure that the SPI master can identify that the register contents are all lost and the configuration registers needs to be rewritten. It is recommended that the bit be read if any under-voltage fault is detected.