ZHCSTG6A July   2023  – October 2023 TPS25984

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. 说明(续)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew Rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power-Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 FET Health Monitoring
      15. 8.3.15 Single Point Failure Mitigation
        1. 8.3.15.1 IMON Pin Single Point Failure
        2. 8.3.15.2 ILIM Pin Single Point Failure
        3. 8.3.15.3 IREF Pin Single Point Failure
        4. 8.3.15.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
      3. 9.1.3 Multiple eFuses, Parallel Connection With PMBus
      4. 9.1.4 Digital Telemetry Using External Microcontroller
    2. 9.2 Typical Application: 12-V, 3.3-kW Power Path Protection in Data Center Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Transient Protection
      2. 9.4.2 Output short-Circuit Measurements
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Detailed Design Procedure

  • Determining the number of eFuse devices to be used in parallel

    By factoring in a small variation in the junction to ambient thermal resistance (RθJA), a single TPS25984x eFuse is rated at a maximum steady state DC current of 55 A at an ambient temperature of 70°C. Therefore, Equation 26 can be used to calculate the number of devices (N) to be in parallel to support the maximum steady state DC load current (ILOAD(max)), for which the solution must be designed.

    Equation 26. N I O U T m a x   A 55   A

    According to Table 9-1, IOUT(max) is 275 A. Therefore, five (5) TPS25984 eFuses are connected in parallel.

  • Setting up the primary and secondary devices in a parallel configuration

    The MODE pin is used to configure one TPS25984x eFuse as the primary device in a parallel chain along with the other TPS25984x eFuses as the secondary devices. As a result, some of the TPS25984 pin functionalities can be changed to facilitate primary and secondary configuration as described in Multiple Devices, Parallel Connection.

    Leaving the MODE pin open configures the corresponding device as the primary one. For the secondary devices, this pin must be connected to GND.

  • Selecting the CDVDT capacitor to control the output slew rate and start-up time

    For a robust design, the junction temperature of the device must be kept below the absolute maximum rating during both dynamic (start-up) and steady-state conditions. Typically, dynamic power stresses are orders of magnitude greater than static stresses, so it is crucial to establish the right start-up time and inrush current limit for the capacitance in the system and the associated loads to avoid thermal shutdown during start-up.

    Table 9-2 summarizes the formulas for calculating the average inrush power loss on the eFuses in the presence of different loads during start-up if the power good (PG) signal is not used to turn on all the downstream loads.

    Table 9-2 Calculation of Average Power Loss During Inrush
    Type of Loads During Start-Up Expressions to Calculate the Average Inrush Power Loss
    Only output capacitor of CLOAD (µF)
    Equation 27. V I N 2 C L O A D 2 T s s
    Output capacitor of CLOAD (µF) and constant resistance of RLOAD(Startup) (Ω) with turn-ON threshold of VRTH (V)
    Equation 28. V I N 2 C L O A D 2 T s s + V I N 2 R L O A D ( S t a r t u p ) 1 6 - 1 2 V R T H V I N 2 + 1 3 V R T H V I N 3
    Output capacitor of CLOAD (µF) and constant current of ILOAD(Startup) (A) with turn-ON threshold of VCTH (V)
    Equation 29. V I N 2 C L O A D 2 T s s + V I N I L O A D ( S t a r t u p ) 1 2 - V C T H V I N + 1 2 V C T H V I N 2
    Output capacitor of CLOAD (µF) and constant power of PLOAD(Startup) (W) with turn-ON threshold of VPTH (V)
    Equation 30. V I N 2 C L O A D 2 T s s + P L O A D ( S t a r t u p ) ln V P T H V I N + V P T H V I N - 1

    Where VIN is the input voltage and Tss is the start-up time.

    With the different combinations of loads during start-up, the total average inrush power loss (PINRUSH) can be calculated using the formulas described in Table 9-2. For a successful start-up, the system must satisfy the condition stated in Equation 31.

    Equation 31. P I N R U S H W T s s s < 10 × N

    Where N denotes the number of eFuses in parallel and 10 W√s is the SOA limit of a single TPS25984x eFuse. This equation can be used to obtain the maximum allowed Tss.

    Note:

    TI recommends to use a Tss in the range of 5 ms to 120 ms to prevent start-up issues.

    A capacitor (CDVDT) must be added at the DVDT pin to GND to set the required value of Tss as calculated above. Equation 32 is used to compute the value of CDVDT. The DVDT pins of all the eFuses in a parallel chain must be connected together.

    Equation 32. C D V D T p F = 42000 V I N V / T s s m s

    In this design example, CLOAD = 50 mF, RLOAD(Startup) = 0.48 Ω, VRTH = 0 V, VIN = 12 V, and Tss = 10 ms. PINRUSH is calculated to be 410 W using the equations provided in the Table 9-2. It can be verified that the system satisfies condition stated in Equation 31 and therefore capable of a successful start-up. If Equation 31 does not hold true, start-up loads or Tss must be tuned to prevent chances of thermal shutdown during start-up. Using VIN = 12 V, Tss = 10 ms, and Equation 32, the required CDVDT value can be calculated to be 35 nF. The closest standard value of CDVDT is 33 nF with 10% tolerance and DC voltage rating of 25 V.

    Note:

    In some systems, there can be active load circuits (for example, DC-DC converters) with low turn-on threshold voltages which can start drawing power before the eFuse has completed the inrush sequence. This action can cause additional power dissipation inside the eFuse during start-up and can lead to thermal shutdown. TI recommends using the Power Good (PG) pin of the eFuse to enable and disable the load circuit. This action ensures that the load is turned on only when the eFuse has completed its start-up and is ready to deliver full power without the risk of hitting thermal shutdown.

  • Selecting the RIREF resistor to set the reference voltage for overcurrent protection and active current sharing

    In this parallel configuration, the IREF internal current source (IIREF) of the primary eFuse interacts with the external IREF pin resistor (RIREF) to generate the reference voltage (VIREF) for the overcurrent protection and active current sharing blocks. When the voltage at the IMON pin (VIMON) is used as an input to an ADC to monitor the system current or to implement the Platform Power Control ( Intel® PSYS) functionality inside the VR controller, VIREF must be set to half of the maximum voltage range of the ISYS_IN input of the controller. This action provides the necessary headroom and dynamic range for the system to accurately monitor the load current up to the fast-trip threshold (2 × IOCP). Equation 33 is used to calculate the value of RIREF.

    Equation 33. V I R E F = I I R E F × R I R E F

    In this design example, VIREF is set at 1 V. With IIREF = 24.99 µA (typical), we can calculate the target RIREF to be 40 kΩ. The closest standard value of RIREF is 40.2 kΩ with 0.1% tolerance and power rating of 100 mW. For improved noise immunity, place a 1000-pF ceramic capacitor from the IREF pin to GND. The IREF pins of all the eFuses in a parallel chain must be connected together.

    Note:

    Maintain VIREF within the recommended voltage to ensure proper operation of overcurrent detection circuit.

  • Selecting the RIMON resistor to set the overcurrent (circuit-breaker) and fast-trip thresholds during steady-state

    TPS25984x eFuse responds to the output overcurrent conditions during steady-state by turning off the output after a user-adjustable transient fault blanking interval. This eFuse continuously senses the total system current (IOUT) and produces a proportional analog current output (IIMON) on the IMON pin. This generates a voltage (VIMON) across the IMON pin resistor (RIMON) in response to the load current, which is defined as Equation 34.

    Equation 34. V I M O N = I O U T × G I M O N × R I M O N

    GIMON is the current monitor gain (IIMON : IOUT), whose typical value is 18.13 µA/A. The overcurrent condition is detected by comparing the VIMON against the VIREF as a threshold. The circuit-breaker threshold during steady-state (IOCP) can be calculated using Equation 35.

    Equation 35. I O C P = V I R E F G I M O N × R I M O N

    In this design example, IOCP is considered to be around 1.1 times IOUT(max). Hence, IOCP is set at 300 A, and RIMON can be calculated to be 183.8 Ω with GIMON as 18.13 µA/A and VIREF as 1 V. The nearest value of RIMON is 182 Ω with 0.1% tolerance and power rating of 100 mW. For noise reduction, place a 22-pF ceramic capacitor across the IMON pin and GND. The IMON pins of all the eFuses in a parallel chain must be connected together.

    Note:

    A system output current (IOUT) must be considered when selecting RIMON, not the current carried by each device.

  • Selecting the RILIM resistor to set the current limit and fast-trip thresholds during start-up and the active sharing threshold during steady-state

    RILIM is used in setting up the active current sharing threshold during steady-state and the overcurrent limit during startup among the devices in a parallel chain. Each device continuously monitors the current flowing through it (IDEVICE) and outputs a proportional analog output current on its own ILIM pin. This in turn produces a proportional voltage (VILIM) across the respective ILIM pin resistor (RILIM), which is expressed as Equation 36.

    Equation 36. V I L I M = I D E V I C E × G I L I M × R I L I M

    GILIM is the current monitor gain (IILIM : IDEVICE), whose typical value is 18.13 μA/A.

    • Active current sharing during steady-state: This mechanism operates only after the device reaches steady-state and acts independently by comparing its own load current information (VILIM) with the Active Current Sharing reference (CLREFLIN) threshold, defined as Equation 37.

      Equation 37. C L R E F L I N = 1.1 × V I R E F 3

      Therefore, RLIM must be calculated using Equation 38 to define the active current sharing threshold as IOCP/N, where N is the number of devices in parallel. Using N = 5, RIMON = 182 Ω, and Equation 38, RILIM can be calculated to be 333.3 Ω. The closest standard value of 332 Ω with 0.1% tolerance and power rating of 100 mW resistances are selected as RILIM for each device.

      Equation 38. R I L I M = 1.1 × N × R I M O N 3
      Note:

      To determine the value of RILIM, Equation 39 must be used if a different threshold for active current sharing (ILIM(ACS)) than IOCP/N is desired.

      Equation 39. R I L I M = 1.1 × V I R E F 3 × G I L I M × I L I M ( A C S )

      When computing the current limit threshold during start-up in the next sub-section, ensure to use this RILIM value.

    • Overcurrent limit during start-up: During inrush, the overcurrent condition for each device is detected by comparing its own load current information (VILIM) with a scaled reference voltage as depicted in Equation 40.

      Equation 40. C L R E F S A T = 0.7 × V I R E F 3

      The current limit threshold during start-up can be calculated using Equation 41.

      Equation 41. I I L I M S t a r t u p = C L R E F S A T G I L I M × R I L I M

      By using a RILIM value of 332 Ω for each device, the start-up current is limited to around 38 A for each device.

      Note:

      The active current limit block employs a foldback mechanism during start-up based on VOUT. When VOUT is below the foldback threshold (VFB) of 2 V, the current limit threshold is further lowered.

  • Selecting the CITIMER capacitor to set the overcurrent blanking timer

    An appropriate capacitor can be connected at the ITIMER pin to ground to adjust the duration for which the load transients above the circuit-breaker threshold are allowed. The transient overcurrent blanking interval can be calculated using Equation 42.

    Equation 42. t I T I M E R m s = C I T I M E R n F × V I T I M E R V I I T I M E R μ A

    Where tITIMER is the transient overcurrent blanking timer and CITIMER is the capacitor connected between ITIMER pin of the primary device and GND. IITIMER = 2.05 µA and ΔVITIMER = 1.5 V. A 22-nF capacitor with 10% tolerance and DC voltage rating of 25 V is used as the CITIMER for the primary device in this design, which results in 16.5 ms of tITIMER. The ITIMER pin for all the secondary devices is left open.

  • Selecting the resistors to set the undervoltage lockout threshold

    The undervoltage lockout (UVLO) threshold is adjusted by employing the external voltage divider network of R1 and R2 connected between IN, EN/UVLO, and GND pins of the device as described in Undervoltage protection section. The resistor values required for setting up the UVLO threshold are calculated using Equation 43.

    Equation 43. V I N U V = V U V L O R R 1 + R 2 R 2

    To minimize the input current drawn from the power supply, TI recommends using higher resistance values for R1 and R2. The current drawn by R1 and R2 from the power supply is IR12 = VIN / (R1 + R2). However, the leakage currents due to external active components connected to the resistor string can add errors to these calculations. So, the resistor string current, IR12 must be 20 times greater than the leakage current at the EN/UVLO pin (IENLKG). From the device electrical specifications, IENLKG is 0.1 µA (maximum) and UVLO rising threshold VUVLO(R) = 1.2 V. From the design requirements, VINUVLO = 10.8 V. First choose the value of R1 = 1 MΩ and use Equation 13 to calculate R2 = 125 kΩ. Use the closest standard 1 % resistor values: R1 = 1 MΩ and R2 = 124 kΩ. For noise reduction, place a 1000-pF ceramic capacitor across the EN/UVLO pin and GND.

  • Selecting the R-C filter between VIN and VDD

    VDD pin is intended to power the internal control circuitry of the eFuse with a filtered and stable supply, not affected by system transients. Therefore, use an R (10 Ω) – C (2.2 µF) filter from the input supply (IN pin) to the VDD pin. This helps to filter out the supply noises and to hold up the controller supply during severe faults such as short-circuit at the output. In a parallel chain, this R-C filter must be employed for each device.

  • Selecting the pullup resistors and power supplies for SWEN, PG, and FLT pins

    FLT and PG are the open drain outputs. If these logic signals are used, the corresponding pins must be pulled up to the appropriate voltages (< 5 V) through 10-kΩ pullup resistances.

    CAUTION:

    SWEN pin must be pulled up to a voltage in the range of 2.5 V to 5 V through a 100-kΩ resistance. This pullup power supply must be generated from the input to the eFuse and available before the eFuse is enabled, without which the eFuse does not start up.

    PG pin must be pulled up to a voltage in the range of 2.5 V to 5 V through a 100-kΩ resistance.

  • Selection of TVS diode at input and Schottky diode at output

    In the case of a short circuit and overload current limit when the device interrupts a large amount of current instantaneously, the input inductance generates a positive voltage spike on the input, whereas the output inductance creates a negative voltage spike on the output. The peak amplitudes of these voltage spikes (transients) are dependent on the value of inductance in series with the input or output of the device. Such transients can exceed the absolute maximum ratings of the device and eventually lead to failures due to electrical overstress (EOS) if appropriate steps are not taken to address this issue. Typical methods for addressing this issue include:

    1. Minimize lead length and inductance into and out of the device.

    2. Use a large PCB GND plane.

    3. Addition of the Transient Voltage Suppressor (TVS) diodes to clamp the positive transient spike at the input.

    4. Using Schottky diodes across the output to absorb negative spikes.

    Refer to TVS Clamping in Hot-Swap Circuits and Selecting TVS Diodes in Hot-Swap and ORing Applications for details on selecting an appropriate TVS diode and the number of TVS diodes to be in parallel to effectively clamp the positive transients at the input below the absolute maximum ratings of the IN pin (20 V). These TVS diodes also help to limit the transient voltage at the IN pin during the Hot Plug event. Four (4) SMDJ12A are used in parallel in this design example.

    Note:

    Maximum Clamping Voltage VC specification of the selected TVS diode at Ipp (10/1000 μs) (V) must be lower than the absolute maximum rating of the power input (IN) pin for safe operation of the eFuse.

    Selection of the Schottky diodes must be based on the following criteria:

    • The non-repetitive peak forward surge current (IFSM) of the selected diode must be more than the fast-trip threshold (2 × IOCP(TOTAL)). Two or more Schottky diodes in parallel must be used if a single Schottky diode is unable to meet the required IFSM rating. Equation 44 calculates the number of Schottky diodes (NSchottky) that must be in parallel.
      Equation 44. N S c h o t t k y > 2 × I O C P T O T A L I F S M
    • Forward Voltage Drop (VF) at near to IFSM must be as small as possible. Ideally, the negative transient voltage at the OUT pin must be clamped within the absolute maximum rating of the OUT pin (–1 V).

    • DC Blocking Voltage (VRM) must be more than the maximum input operating voltage.

    • Leakage current (IR) must be as small as possible.

    Three (3) SBR10U45SP5 are used in parallel in this design example.

  • Selecting CIN and COUT

    TI recommends to add ceramic bypass capacitors to help stabilize the voltages on the input and output. The value of CIN must be kept small to minimize the current spike during hot-plug events. For each device, 0.1 µF of CIN is a reasonable target. Because COUT does not get charged during hot-plug, a larger value such as 2.2 µF can be used at the OUT pin of each device.