ZHCSPB6D July   2022  – April 2024 TPS1211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS12111-Q1 Only)
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection with Auto-Retry
        2. 8.3.3.2 Overcurrent Protection with Latch-Off
        3. 8.3.3.3 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 Overvoltage (OV) and Undervoltage Protection (UVLO)
      6. 8.3.6 Remote Temperature Sensing and Protection (DIODE)
      7. 8.3.7 Output Reverse Polarity Protection
      8. 8.3.8 TPS1211x-Q1 as a Simple Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving Zonal Controller Loads on 12-V Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Reverse Polarity Protection with TPS12110-Q1
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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6.6 Switching Characteristics

TJ = –40℃ to +125℃; typical values at TJ = 25°C, V(VS) = V(CS+) = V(CS–) = 12 V, V(BST – SRC) = 12 V, V(SRC) = 0 V, VSNS = Voltage across RSNS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPU(INP_H) INP Turn ON propogation Delay INP ↑ to PU  ↑, CL = 47 nF 1 2 µs
tPD(INP_L) INP Turn OFF propogation Delay INP ↓ to PD  ↓, CL = 47 nF 1 µs
tG(INP_G_H) INP_G Turn ON propogation Delay INP_G ↑ to G  ↑, CL = 1 nF 21 µs
tG(INP_G_L) INP_G Turn OFF propogation Delay INP_G ↓ to G  ↓, CL = 1 nF 0.55 0.8 µs
tPD(EN_OFF) EN Turn OFF Propogation Delay  EN ↓ to PD  ↓, CL = 47 nF 3.2 5 µs
tPD(UVLO_OFF) UVLO Turn OFF Propogation Delay  UVLO ↓ to PD  ↓, CL = 47 nF 3.5 6 µs
tPD(VS_OFF) PD Turn OFF delay during input supply (VS) interruption VS ↓ V(VS_PORF) to PD  ↓, CL = 47 nF, INP = EN/UVLO = 2 V 54 µs
tPU(VS_ON) PU Turn ON delay during input supply (VS) recovery VS ↑ V(VS_PORR) to PU  ↑, CL = 47 nF, INP = EN/UVLO = 2 V, V(BST–SRC) > V(BST_UVLOR) 328 465 µs
tPD(OV_OFF) OV Turn Off progopation Delay OV ↑ to PD  ↓, CL = 47 nF 2.6 4 µs
tSC Short-circuit protection propogation Delay (VCS+ – VCS–) ↑ V(SNS_SCP) to PD ↓, CL = 47 nF, TPS12111-Q1 and TPS12112-Q1 Only 1.16 1.6 µs
Short-circuit protection propogation Delay (VCS+ – VCS–) ↑ V(SNS_SCP)  to PD  ↓, CL = 47 nF, TPS12110–Q1 Only 4 5 µs
tOC Over current protection delay  (VCS+ – VCS–) ↑ V(SNS_WRN) to PD ↓, CL = 47 nF, CTMR = 0 nF 25 30 µs
Over current protection delay  (VCS+ – VCS–) ↑ V(SNS_WRN) to PD ↓, CL = 47 nF, CTMR = 22 nF 370 µs
t(FLT_I_ASSERT) FLT_I assertion delay CTMR = 22 nF 340 µs
t(FLT_I_DEASSERT) FLT_I de-assertion delay 260 µs
t(FLT_T)AR TSD Auto-retry  TPS12110-Q1 and TPS12112-Q1 Only 512 msec