ZHCSO53G August   2010  – June 2021 TPD2EUSB30 , TPD2EUSB30A , TPD4EUSB30

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on D+, D- Pins
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VRWMReverse stand-off voltage (D+ and D- pins)TPD2EUSB30, TPD4EUSB305.5V
TPD2EUSB30A3.6V
VclampClamp voltageD+,D– pins to ground,IIO = 1 A8V
IIOCurrent from IO port to supply pinsVIO = 2.5 V,ID = 8 mA0.010.1μA
VDDiode forward voltageD+,D– pins,
lower clamp diode,
VIO = 2.5 V,
ID = 8 mA
0.60.80.95V
RdynDynamic resistanceD+,D– pinsI = 1 A0.6
CIO-IOCapacitance IO to IOD+,D– pinsVIO = 2.5 V; ƒ = 100 kHz0.05pF
CIO-GNDCapacitance IO to GNDD+,D– pins (DRT)VIO = 2.5 V; ƒ = 100 kHz0.7pF
D1+, D1-,
D2+, D2- (DQA )
0.8
VBRBreak-down voltage, TPD2EUSB30, TPD4EUSB30IIO = 1 mA7V
Break-down voltage, TPD2EUSB30AIIO = 1 mA4.5V